Patents by Inventor Fumiyoshi Kawashiro
Fumiyoshi Kawashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105561Abstract: According to one embodiment, there is provided a semiconductor device including a chip, a drain electrode arranged on a first surface of the chip, a source electrode arranged on a second surface provided on a back side of the first surface of the chip and having a front surface on a device bottom surface, a gate electrode having a front surface on the device bottom surface, and a wire connecting a first region of the gate electrode to a second region on the second surface of the chip.Type: ApplicationFiled: September 7, 2023Publication date: March 28, 2024Inventor: Fumiyoshi KAWASHIRO
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Publication number: 20240105558Abstract: According to one embodiment, there is provided a semiconductor device including a chip, and a gate electrode connected to a gate electrode pad provided on the chip. The gate electrode includes an external exposed portion having an external exposed surface that is flush with an external exposed surface of a sealing resin, and a gate electrode pad connection portion continuous with the external exposed portion and connected to the gate electrode pad, the gate electrode pad connection portion including a portion sandwiched between the gate electrode pad and a part of the sealing resin.Type: ApplicationFiled: March 6, 2023Publication date: March 28, 2024Inventors: Eitaro MIYAKE, Fumiyoshi KAWASHIRO
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Patent number: 11923270Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.Type: GrantFiled: September 2, 2021Date of Patent: March 5, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Tatsuya Kobayashi, Fumiyoshi Kawashiro, Hisashi Tomita
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Publication number: 20230298976Abstract: A semiconductor of an embodiment includes a lead frame including a first bed; a first post; a second post; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip, a first film thickness of the first bonding material portion being thinner than a second film thickness of the second bonding material portion; a first connector; a second bonding material; and a third bonding material.Type: ApplicationFiled: September 8, 2022Publication date: September 21, 2023Inventor: Fumiyoshi KAWASHIRO
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Publication number: 20230081341Abstract: A semiconductor device according to the present embodiment comprises a semiconductor chip comprising a first face and a second face on an opposite side to the first face, and comprising a first electrode in the first face. A first metallic member comprises a first opposed face facing the first electrode and being larger in a profile than the first electrode, the first metallic member comprising a first protruded portion protruded from the first opposed face toward the first electrode and electrically connected to the first electrode. An insulating member coats the semiconductor chip and the first metallic member.Type: ApplicationFiled: February 16, 2022Publication date: March 16, 2023Inventor: Fumiyoshi KAWASHIRO
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Patent number: 11476223Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.Type: GrantFiled: January 29, 2020Date of Patent: October 18, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Daisuke Koike, Fumiyoshi Kawashiro
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Publication number: 20220301988Abstract: According to one embodiment, a semiconductor device includes: a semiconductor chip; a mold resin provided over the semiconductor chip, and having at least a recess along its bottom surface; and a first terminal provided along a first upper surface of the recess and electrically connected to the semiconductor chip.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Fumiyoshi KAWASHIRO
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Patent number: 11437339Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.Type: GrantFiled: January 29, 2020Date of Patent: September 6, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Daisuke Koike, Fumiyoshi Kawashiro
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Publication number: 20220093485Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.Type: ApplicationFiled: September 2, 2021Publication date: March 24, 2022Inventors: Tatsuya Kobayashi, Fumiyoshi Kawashiro, Hisashi Tomita
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Patent number: 11276629Abstract: A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the sType: GrantFiled: January 30, 2020Date of Patent: March 15, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Fumiyoshi Kawashiro
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Patent number: 11264348Abstract: A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.Type: GrantFiled: January 29, 2020Date of Patent: March 1, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Fumiyoshi Kawashiro
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Publication number: 20210074666Abstract: A semiconductor device of embodiments includes a substrate; a semiconductor chip provided above the substrate; a first ultrasonic bonding portion provided between the substrate and the semiconductor chip; a first terminal plate electrically connected to the semiconductor chip via the first ultrasonic bonding portion, the first ultrasonic bonding portion being provided on the substrate, and the first terminal plate having a first surface facing the semiconductor chip; and a first adhesive layer provided on the first surface, and the first adhesive layer containing a first adhesive.Type: ApplicationFiled: January 29, 2020Publication date: March 11, 2021Inventor: Fumiyoshi Kawashiro
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Publication number: 20210066234Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.Type: ApplicationFiled: January 29, 2020Publication date: March 4, 2021Inventors: Daisuke Koike, Fumiyoshi Kawashiro
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Publication number: 20210035893Abstract: A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the sType: ApplicationFiled: January 30, 2020Publication date: February 4, 2021Inventor: Fumiyoshi Kawashiro
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Publication number: 20190189584Abstract: According to one embodiment, semiconductor device includes a semiconductor layer, an electrode provided on the semiconductor layer, and a bonding wire connected to the electrode, wherein the electrode comprises a first metal layer containing copper, a second metal layer containing aluminum, provided between the first metal layer and the semiconductor layer, and a third metal layer provided between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, and the thickness of the first metal layer is larger than the thickness of the second metal layer and larger than the thickness of the third metal layer.Type: ApplicationFiled: August 31, 2018Publication date: June 20, 2019Inventor: Fumiyoshi KAWASHIRO
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Publication number: 20180068964Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Takehiko MAEDA, Akira Yajima, Satoshi Itou, Fumiyoshi Kawashiro
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Patent number: 9853005Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film.Type: GrantFiled: July 6, 2015Date of Patent: December 26, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takehiko Maeda, Akira Yajima, Satoshi Itou, Fumiyoshi Kawashiro
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Publication number: 20160013142Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film.Type: ApplicationFiled: July 6, 2015Publication date: January 14, 2016Inventors: Takehiko MAEDA, Akira YAJIMA, Satoshi ITOU, Fumiyoshi KAWASHIRO
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Publication number: 20130005090Abstract: A semiconductor device manufacturing method includes cutting a resin sealing body into a plurality of pieces, the resin sealing body including a plurality of semiconductor chips mounted on a wiring board, a heat spreader disposed above the plurality of the semiconductor chips, and a sealing resin filled between the wiring board and the heat spreader, wherein the cutting the resin sealing body includes shaving the resin sealing body from a side of the heat spreader, and shaving the resin sealing body from a side of the wiring board, wherein the shaving the resin sealing body from the side of the wiring board is carried out after the shaving from the side of the heat spreader, and wherein the resin sealing body is completely cut off by the shaving from the side of the wiring board, and mounting a group of ball-like electrodes at a back side of the wiring board.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Inventors: Yuko Sato, Takehiko Maeda, Fumiyoshi Kawashiro
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Patent number: 8232652Abstract: A semiconductor device includes: an interconnection substrate on which a semiconductor chip is mounted; electrodes formed on a surface of the interconnection substrate; and solder bumps formed on the electrodes. The solder bump includes a base section and a surface layer section that covers the base section. The surface layer section includes conductive metal selected from the group consisting of Cu, Ni, Au, and Ag, and Sn at least and a ratio of the number of atoms of the conductive metal to the number of Sn atoms per a unit volume is more than 0.01.Type: GrantFiled: March 22, 2011Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventor: Fumiyoshi Kawashiro