Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.

Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

Abstract: Disclosed herein is a memory module that includes a register buffer and a memory chip each mounted on a module substrate. Each of the command address output terminals belonging to the first group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the first group provided on the memory chip through associated ones of the plurality of contact plugs and the first wiring layer. Each of the command address output terminals belonging to the second group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the second group provided on the memory chip through associated ones of the plurality of contact plugs and the second wiring layer.

Abstract: A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.

Abstract: A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

Abstract: A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.

Abstract: A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.

Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

Abstract: A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.

Abstract: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

Abstract: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

Abstract: A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.

Abstract: A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected

Abstract: A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.