Patents by Inventor Fung Song Lee

Fung Song Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for double-patterning-compliant standard cell design
    Patent number: 9747402
    Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
  • Methods for Double-Patterning-Compliant Standard Cell Design
    Publication number: 20150095870
    Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
  • Methods for double-patterning-compliant standard cell design
    Patent number: 8907441
    Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
  • Methods for Double-Patterning-Compliant Standard Cell Design
    Publication number: 20110193234
    Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu