Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Apparatus and method for multi-core dynamically-balanced task processing while maintaining task order in chip multiprocessor platforms. One embodiment of an apparatus includes: a distribution circuitry to distribute, among a plurality of processing units, tasks from one or more workflows; a history list to track all tasks distributed by the distribution circuitry; an ordering queue to store one or more sub-tasks received from a first processing unit as a result of the first processing unit processing a first task; and wherein, responsive to a detection that all sub-tasks of the first task have been received and that the first task is the oldest task for a given parent workflow tracked by the history list, all sub-tasks associated with the first task are to be placed in a replay queue to be replayed in the order in which each sub-task was received.

Abstract: Apparatus and method for multi-core dynamically-balanced task processing while maintaining task order in chip multiprocessor platforms. One embodiment of an apparatus includes: a distribution circuitry to distribute, among a plurality of processing units, tasks from one or more workflows; a history list to track all tasks distributed by the distribution circuitry; an ordering queue to store one or more sub-tasks received from a first processing unit as a result of the first processing unit processing a first task; and wherein, responsive to a detection that all sub-tasks of the first task have been received and that the first task is the oldest task for a given parent workflow tracked by the history list, all sub-tasks associated with the first task are to be placed in a replay queue to be replayed in the order in which each sub-task was received.

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Abstract: Provided are methods for introducing a molecule of interest into a plant cell comprising a cell wall. Methods are provided for genetically or otherwise modifying plants and for treating or preventing disease in plant cells comprising a cell wall.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Provided are methods for introducing a molecule of interest into a plant cell comprising a cell wall. Methods are provided for genetically or otherwise modifying plants and for treating or preventing disease in plant cells comprising a cell wall.

Abstract: Provided are methods for introducing a molecule of interest into a plant cell comprising a cell wall. Methods are provided for genetically or otherwise modifying plants and for treating or preventing disease in plant cells comprising a cell wall.

Abstract: Methods and systems for processing touch inputs are disclosed. The invention in one respect includes reading data from a multi-touch sensing device such as a multi-touch touch screen where the data pertains to touch input with respect to the multi-touch sensing device, and identifying at least one multi-touch gesture based on the data from the multi-touch sensing device and providing an appropriate multi-haptic response.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: Provided are methods for introducing a molecule of interest into a plant cell comprising a cell wall. Methods are provided for genetically or otherwise modifying plants and for treating or preventing disease in plant cells comprising a cell wall.

Abstract: Methods and systems for processing touch inputs are disclosed. The invention in one respect includes reading data from a multi-touch sensing device such as a multi-touch touch screen where the data pertains to touch input with respect to the multi-touch sensing device, and identifying at least one multi-touch gesture based on the data from the multi-touch sensing device and providing an appropriate multi-haptic response.

Abstract: A wetted wall cyclone system for sampling an aerosol. In an embodiment, the system comprises a cyclone body including an inlet end, an outlet end, and an inner flow passage extending therebetween. In addition, the system comprises a cyclone inlet tangentially coupled to the cyclone body proximal the inlet end. The cyclone inlet includes an inlet flow channel in fluid communication with the inner flow passage of the cyclone body. Further, the system comprises a skimmer coaxially coupled to the outlet end of the cyclone body. The skimmer comprises a separation end extending into the outlet end of the cyclone body, a free end distal the outlet end of the cyclone body, and an inner exhaust channel in fluid communication with the inner flow passage of the cyclone body. Still further, the system comprises means for reducing the temperature of at least a portion of the cyclone body.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: A wetted wall cyclone system for sampling an aerosol. In an embodiment, the system comprises a cyclone body including an inlet end, an outlet end, and an inner flow passage extending therebetween. In addition, the system comprises a cyclone inlet tangentially coupled to the cyclone body proximal the inlet end. The cyclone inlet includes an inlet flow channel in fluid communication with the inner flow passage of the cyclone body. Further, the system comprises a skimmer coaxially coupled to the outlet end of the cyclone body. The skimmer comprises a separation end extending into the outlet end of the cyclone body, a free end distal the outlet end of the cyclone body, and an inner exhaust channel in fluid communication with the inner flow passage of the cyclone body. Still further, the system comprises means for reducing the temperature of at least a portion of the cyclone body.

Abstract: The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor, wherein at least one bit of data is a logic ONE. An output signal is formed from the one bit of data in the register. The output signal is sent as an interrupt signal to an interrupt terminal of the second processor for synchronizing the first processor with the second processor. The method may be used with a memory mapped register or an off-core register. The first and second processors may each be a digital signal processor (DSP) or any other type of processor.

Abstract: A bowling lane maintenance apparatus includes a transfer roller and a dressing oil tank configured to contain dressing oil. A wick is configured to pass dressing oil from the tank to the transfer roller. A buffer brush is configured to receive dressing oil from the transfer roller and spread the dressing oil on a bowling lane. The wick may comprise a foam material having a first region having a first capillarity and a second region having a second capillarity differing from the first capillarity. The wick may also be maintained in contact with the transfer roller.