Abstract: A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition.

Abstract: A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition.

Abstract: In one embodiment, an electronic switch selectively passes an input signal from an input node to an output node based on a switch-control signal. The bulk of at least one transistor in the switch is connected to either the input node or the output node. The switch has two series-connected PMOS transistors connected in parallel with an NMOS transistor. The bulk and source of the first PMOS transistor are connected to the input node, while the bulk and source of the second PMOS transistor are connected to the output node. First and second level shifters ensure that the gates of the first and second PMOS transistors track the voltages at the input and output nodes, respectively. This configuration improves the ability of the switch to receive input voltages outside of the switch's power supply range without adversely affecting operations of the switch.