Abstract: A plurality of switches are disposed about the periphery of a display. The switches input information from a user to a controlled electronic device. By pressing down on any point of the periphery of the display, two switches disposed at the corners adjacent to the pressed side are operated. A cursor, responsively coupled to the switches, moves towards the frame side that is pressed. Alternatively, displayed text can be made to move away from the side that is pressed. Further, by pressing down simultaneously on two points disposed on opposite sides of the display, a display item that is associated with the present cursor position is selected.

Abstract: The disclosed invention relates to a system for restricting radio frequency transmissions within a restricted area and more particularly to a mechanism for overriding the restriction of radio frequency transmissions within a restricted area using an override mechanism. A restricted area is defined wherein all radio frequency transmissions are restricted. Within the restricted a plurality of cellular telephones is disposed, each with a radio frequency transmitter and a radio frequency receiver. An emergency override is also disposed within the restricted area, the emergency override capable of selectively enabling communications of a selected subset of the cellular telephones disposed within the restricted area.

Abstract: The disclosed invention relates to a system for restricting radio frequency transmissions within a restricted area and more particularly to a mechanism for overriding the restriction of radio frequency transmissions within a restricted area using an override mechanism. A restricted area is defined wherein all radio frequency transmissions are restricted. Within the restricted a plurality of cellular telephones is disposed, each with a radio frequency transmitter and a radio frequency receiver. An emergency override is also disposed within the restricted area, the emergency override capable of selectively enabling communications of a selected subset of the cellular telephones disposed within the restricted area.

Abstract: A system, consisting of an ultrasonic transmitter and a receiver, is described for controlling certain electronic sound-generating and radio-frequency-generating devices. In restricted areas where the audible sound generated by these electronic devices is objectionable, one or more ultrasonic transmitters are placed to blanket the area, each emitting an ultrasonic signal periodically. In electronic devices having ultrasonic receivers, the receipt of this signal prevents the electronic device from generating or reproducing objectionable audible sound for a short period of time after receipt of this ultrasonic signal, which is slightly longer than the period in which the ultrasonic signal is sent.

Abstract: A system, consisting of an ultrasonic transmitter and a receiver, is described for controlling certain electronic sound-generating and radio-frequency-generating devices. In restricted areas where the audible sound generated by these electronic devices is objectionable, one or more ultrasonic transmitters are placed to blanket the area, each emitting an ultrasonic signal periodically. In electronic devices having ultrasonic receivers, the receipt of this signal prevents the electronic device from generating or reproducing objectionable audible sound for a short period of time after receipt of this ultrasonic signal, which is slightly longer than the period in which the ultrasonic signal is sent.

Abstract: A system, apparatus and method for inhibiting the ringer of a cellular telephone within a noise sensitive area includes a transmitter for generating a control signal within the area. A receiver within the cellular telephone generates a mute signal during reception of the control signal which inhibits operation of the telephone ringer circuit while the telephone is in the noise sensitive area. In an alternate embodiment, a transmitter of limited range is placed at each entrance to the noise sensitive area and the ringer circuit is inhibited upon momentarily receiving the control signal entering the area, and activated upon momentarily receiving the control signal exiting the area.

Abstract: The invention includes a dynamic storage device requiring periodic refresh and including logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, then a logical operation is performed on the refresh data before application to the write amplifier, allowing implementation of associative data base searching by cyclically executing data compare and other logical operations within the refresh circuitry. Graphics systems using such devices allow less-expensive, faster, graphics display using a scan-line rendering system.

Abstract: An MPEG-1 or an MPEG-2 motion compensation vector encoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry, including ROMs, designed to implement residue arithmetic to calculate sum squared error in a parallel pipelined fashion. A residue-to-binary converter is implemented using distributed arithmetic and a reduction circuit that removes powers of two times the modulus M, both of which use carry save arithmetic operators. An improved ROM-accumulator, used in the residue-to-binary converter, is implemented using carry-save addition within the ROM-accumulator, and ripple-carry or carry-lookahead addition on the output of the ROM-accumulator.

Abstract: Less-expensive, faster graphics display can be achieved by an in-parallel scan-line rendering system using a content-searchable memory based on a modified DRAM requiring periodic refresh that includes logical operation circuitry within the refresh circuitry. Data at individual storage locations of the DRAM are periodically read by a refresh amplifier, then a logical operation is performed on the refresh data before application to the write amplifier, allowing searching by data compare and mathematical operations. The data words of the content-searchable memory are loaded with data defining the multi-axis location of each of the vertices of a polygonal facet of an object in the scene and display information concerning the facet, such as color or texture. Data representing out-of-view objects can be culled, and the remaining objects projected onto a viewport, all through in-parallel manipulations in the content-searchable memory.

Abstract: A dynamic storage device requires periodic refresh and includes logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before the data re applied to the write amplifier. That operation allows implementation of associative database searching by cyclically executing "data compare" and other logical operations within the refresh circuitry. A system of content searching may be implemented in any storage device, dynamic or not, in which a comparand may be matched with any of a plurality of subunits of a word, and a storage bit is used to identify any words in which a mismatch occurs.

Abstract: A parallel associative processor is formed from a DRAM circuit whose storage positions are organized into words, which are further subdivided into columns. Each column is associated with a sense amplifier, which is used to perform data refreshing. Comparators are coupled to the sense amplifiers to permit logical operations, including comparisions with external data placed on a bus, to be performed on data addressed and read from the storage positions, including during refresh operations. A latch or flip-flop with control inputs is associated with each word, to hold a match or mismatch signal identifying, in parallel for each word, the results of the logical operations.

Abstract: An MPEG-2 decoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry, including ROMs, designed to implement residue arithmetic to calculate discrete cosine transforms in a pipelined or iterative fashion. A variable-length decoder based on ROM-like PLAs parses the stream of data to separate audio from video data and to direct the necessary operations on the data elements. The decoder and data flow through the system are controlled by a conditional MOVE processor, which is implemented as a data memory.

Abstract: An apparatus and method for synchronizing parallel processors utilizing a lookahead synchronization circuit is provided by the present invention. A five gate logic circuit is formed as a cell and this cell can serve as a node in a tree logic operation circuit. The tree is capable of realizing a variety of fetch-and-operation, priority and operation-and-broadcast primitives and the cell can serve in a carry circuit of a binary adder. The tree may be pruned at any point and the circuit will continue to function for those nodes remaining in the tree. Processing elements are attached to leaf nodes of the tree.

Abstract: The invention is a dynamic storage device requiring periodic refresh, and including logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before application to the write amplifier. This allows implementation of associated data base searching by cyclically executing data compare and other logical operations within the refresh circuitry.

Abstract: The invention is a dynamic storage device requiring periodic refresh, and including logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before application to the write amplifier. This allows implementation of associative data base searching by cyclically executing a data compare operation within the refresh circuitry.

Abstract: A general purpose digital computer whose architecture provides a set of pointer registers at each memory chip to perform stack operations previously performed on the CPU chip. Bidirectional lines interconnect the CPU chip and the memory chips for transmission and reception of data and control signals. Each memory chip has a circuit for incrementing or decrementing the pointer registers in response to a control signal without the transmission of a data signal from the CPU chip to perform a series of stack operations in the memory chip. Addressable registers are provided in each memory chip for identifying the memory chip (PAGE), storing a mode vector (MODE), and counting the number of times the memory controller was addressed (TIME).