Patents by Inventor G. Jonathan Kluth

G. Jonathan Kluth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6878559
    Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: April 12, 2005
    Assignees: Applied Materials, Inc., Advanced Micro Devices, Inc.
    Inventors: Peter G. Borden, G. Jonathan Kluth, Eric Paton
  • Publication number: 20040063225
    Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.
    Type: Application
    Filed: September 23, 2002
    Publication date: April 1, 2004
    Inventors: Peter G. Borden, G. Jonathan Kluth, Eric Paton
  • Patent number: 6521501
    Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: February 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeff Erhardt, Bin Yu, G. Jonathan Kluth