Abstract: A method and apparatus to synchronize signals between different clock domains are described.

Abstract: A method and apparatus to synchronize signals between different clock domains are described.

Abstract: Architecture and corresponding methods share resources and synchronize counters in high-speed network integrated circuits. The architecture has at least one counter group comprising several registers, each with two ports. One port receives networking events (e.g., receipt of an-error packet, transmission of a good packet, etc.) via a tri-state bus. The registers in each counter group use a shared hardware memory element, which adds the events for each counter group. The second port is available for asynchronous external read accesses via a second tri-state bus. The architecture synchronizes read requests with events such that read accesses occur during gaps in events. The registers are assigned to several mutually exclusive counter groups such that no two registers in the counter group increment in a basic clock cycle.

Abstract: A method for utilizing an XOR network for testing internal nodes of a die wherein the nodes are connected to the input ports of the XOR network. The nodes are chosen by an iterative algorithm whereby the toggled, but not observed nodes, are partitioned into subsets belonging to a test hierarchy whereby the largest subset in the hierarchy is chosen. Based upon this largest subset, a first and second node set is constructed. A functional test is performed wherein the first and second node set, respectively, are inputs and outputs. The second node set serves as inputs to the XOR network. Deeper levels of hierarchies are created if the functional test on the first an second node sets do not meet a fault coverage criterion, or if the hierarchy level is too large, where the deeper test hierarchy is constructed from the largest subset associated with a less deep hierarchy.