Patents by Inventor Gabriel Padron Wells
Gabriel Padron Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9640625Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.Type: GrantFiled: April 25, 2014Date of Patent: May 2, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Gabriel Padron Wells, Andre P. Labonte, Jing Wan
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Patent number: 9460963Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.Type: GrantFiled: March 26, 2014Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gabriel Padron Wells, Xiang Hu, Guillaume Bouche, Andre Labonte
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Patent number: 9443931Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).Type: GrantFiled: January 5, 2016Date of Patent: September 13, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Hui Zang, Guillaume Bouche, Gabriel Padron Wells
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Patent number: 9401263Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.Type: GrantFiled: September 19, 2013Date of Patent: July 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Xiang Hu, Gabriel Padron Wells, Jack Chao-Hsu Chang, Mingmei Wang, Taejoon Han
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Publication number: 20160155800Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).Type: ApplicationFiled: January 5, 2016Publication date: June 2, 2016Applicant: GLOBALFOUNDRIES Inc.Inventors: Hui ZANG, Guillaume BOUCHE, Gabriel Padron WELLS
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Patent number: 9305785Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.Type: GrantFiled: June 30, 2014Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Gabriel Padron Wells, Xiang Hu
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Patent number: 9276064Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).Type: GrantFiled: November 7, 2014Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Guillaume Bouche, Gabriel Padron Wells
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Publication number: 20160049495Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.Type: ApplicationFiled: August 18, 2014Publication date: February 18, 2016Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
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Patent number: 9252238Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.Type: GrantFiled: August 18, 2014Date of Patent: February 2, 2016Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
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Publication number: 20150380250Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Gabriel Padron Wells, Xiang Hu
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Publication number: 20150311082Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Guillaume Bouche, Andy Chih-Hung Wei, Gabriel Padron Wells, Andre P. Labonte, Jing Wan
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Publication number: 20150303295Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Jing Wan, Xiang Hu, Jinping Liu, Gabriel Padron Wells, Andy Chih-Hung Wei, Guillaume Bouche, Cuiqin Xu
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Publication number: 20150279738Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Gabriel Padron Wells, Xiang Hu, Guillaume Bouche, Andre Labonte
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Patent number: 9147680Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.Type: GrantFiled: July 17, 2013Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
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Publication number: 20150076111Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.Type: ApplicationFiled: September 19, 2013Publication date: March 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Xiang HU, Gabriel PADRON WELLS, Jack Chao-Hsu CHANG, Mingmei WANG, Taejoon HAN
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Publication number: 20150021694Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
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Publication number: 20150024584Abstract: Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Gabriel Padron Wells, Yuan-Hung Liu, Kristina Trevino, Chang Ho Maeng, Taejoon Han