Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.

Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region.

Abstract: Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.

Abstract: An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition. The barrier metal layer prevents lower barrier height metals in the conducting metal layer, for example, from reaching the surface of the gallium nitride material substrate.

Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region.

Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

Abstract: An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.

Abstract: An apparatus comprising a channel layer, a first layer, a hole barrier layer and a second layer is disclosed. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valance band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally comprises a field effect transistor.