Patents by Inventor Gabriel T. Dagani

Gabriel T. Dagani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240020806
    Abstract: A system and method for binning. In some embodiments, the method includes segmenting a first pre-image frame into a first plurality of bins; and processing each of the bins to form a respective pixel subarray, the first plurality of bins including: a first bin having first dimensions, and a second bin having second dimensions, different from the first dimensions.
    Type: Application
    Filed: August 23, 2022
    Publication date: January 18, 2024
    Inventors: Gabriel T. DAGANI, Raun KRISCH
  • Patent number: 11763521
    Abstract: A system and a method are disclosed for varying a pixel-rate functionality of a GPU as an optional feature without an explicit implementation from within an application. User interface (UI) content may be detected in a draw call of an application and a variable-rate shader lookup map may be generated based on the detected UI content. A pixel rate of 3D content may be increased using the variable-rate shader lookup map. Additionally or alternatively, other conditions may be detected for increasing the pixel rate, such as using information in an application profile, detecting high or low luminance values, detecting motion and/or detecting temporal anti-aliasing.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: September 19, 2023
    Inventors: Gabriel T. Dagani, Gregory Bergschneider, David C. Tannenbaum
  • Publication number: 20230177762
    Abstract: A system and a method are disclosed for post-processing variable pixel rate shader output using gradients in a graphics processing unit. A block of pixels is selected that corresponds to a predetermined kernel size for variable rate shading in a draw call of an application. A pixel shader run is instantiated to generate pixel shading values for at least two pixels located within the block of pixels. A gradient output is generated based on an interpolation of the pixel shading values for the at least two pixels over the block of pixels. The predetermined kernel size may include at least one of a 4×2 block of pixels, a 2×4 block of pixels, a 4×4 block of pixels, an 8×4 block of pixels, a 4×8 block of pixels, and an 8×8 block of pixels or larger. The at least two pixels may be corner pixels of the block of pixels.
    Type: Application
    Filed: June 7, 2022
    Publication date: June 8, 2023
    Inventors: Gabriel T. DAGANI, Raun KRISCH
  • Publication number: 20230052075
    Abstract: A system and a method are disclosed for varying a pixel-rate functionality of a GPU as an optional feature without an explicit implementation from within an application. User interface (UI) content may be detected in a draw call of an application and a variable-rate shader lookup map may be generated based on the detected UI content. A pixel rate of 3D content may be increased using the variable-rate shader lookup map. Additionally or alternatively, other conditions may be detected for increasing the pixel rate, such as using information in an application profile, detecting high or low luminance values, detecting motion and/or detecting temporal anti-aliasing.
    Type: Application
    Filed: October 6, 2021
    Publication date: February 16, 2023
    Inventors: Gabriel T. DAGANI, Gregory BERGSCHNEIDER, David C. TANNENBAUM
  • Publication number: 20220301096
    Abstract: A system and a method are disclosed for separating 3D content from 2D UI content for selectively upscaling 3D draw calls. A controller, coupled to a graphics pipeline, determines whether an application supports upscaling and, if so, creates a full-resolution framebuffer for rendering 2D drawcalls bound to the graphics pipeline and a reduced-resolution framebuffer for rendering 3D drawcalls bound to the graphics pipeline. A drawcall is then determined to be a 2D or a 3D drawcall. The controller stores the drawcall in the full-resolution framebuffer if the draw call is a 2D drawcall and stores the drawcall in the reduced-resolution framebuffer if the draw call is a 3D drawcall. The draw stored in the reduced-resolution framebuffer is upscaled to be a full-resolution drawcall, and the 2D draw in the full-resolution framebuffer and the upscaled 3D draw are combined to form a final output.
    Type: Application
    Filed: September 27, 2021
    Publication date: September 22, 2022
    Inventors: Gabriel T. DAGANI, Gregory BERGSCHNEIDER
  • Publication number: 20220301095
    Abstract: A system and a method are disclosed improving forward progress of preempted workloads. A graphics pipeline processes tiles of a first low-priority job. A controller stops the first job by resetting the GPU and preempting the first job with a second job having a higher priority, determine whether the first job has been previously preempted one or more times, and adjust a batch-binning parameter reducing a likelihood that the first job will again be preempted in the current frame. In one embodiment, the controller is configured to stop the first job at a preemption boundary during a draw call or by resetting the GPU. A batch-binning parameter may include postponing sorting primitives into tiles during a binning process, increasing a number of tiles for backend rendering, reducing a quality of anti-aliasing, decreasing a shading rate quality, and/or decreasing input resolution and increasing upscaling of the first job.
    Type: Application
    Filed: June 24, 2021
    Publication date: September 22, 2022
    Inventors: Gabriel T. DAGANI, Christopher P. FRASCATI, FNU GURUPAD, David TANNENBAUM, Rama S.B. HARIHARA, Keshavan VARADARAJAN
  • Publication number: 20220206737
    Abstract: A system and method is disclosed that allows multiple casting devices to work together to populate a large display screen according to the subject matter disclosed herein. The system includes a receiving device that includes two or more screen-cast receivers and a controller. Each screen-cast receiver receives from a corresponding casting device at least a portion of a frame of original content of the corresponding casting device generated in a native resolution of the corresponding casting device. The controller synchronizes each received portion of the frame of the original content of the corresponding casting device to form a video output signal that comprises a combination of each received portion, in addition to any internally generated content derived by the receiving display. A casting device may be a smartphone, a tablet, or a computing device, such as a laptop computer.
    Type: Application
    Filed: March 22, 2021
    Publication date: June 30, 2022
    Inventors: Gabriel T. DAGANI, David C. TANNENBAUM, Christopher P. FRASCATI, Michael PHILLIP
  • Patent number: 11360732
    Abstract: A system and method is disclosed that allows multiple casting devices to work together to populate a large display screen according to the subject matter disclosed herein. The system includes a receiving device that includes two or more screen-cast receivers and a controller. Each screen-cast receiver receives from a corresponding casting device at least a portion of a frame of original content of the corresponding casting device generated in a native resolution of the corresponding casting device. The controller synchronizes each received portion of the frame of the original content of the corresponding casting device to form a video output signal that comprises a combination of each received portion, in addition to any internally generated content derived by the receiving display. A casting device may be a smartphone, a tablet, or a computing device, such as a laptop computer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: June 14, 2022
    Inventors: Gabriel T. Dagani, David C. Tannenbaum, Christopher P. Frascati, Michael Phillip
  • Patent number: 11321907
    Abstract: A system and a method are disclosed that optimizes a graphics driver. The system may be embodied as a computing device that includes a storage that is internal to the computing device, a graphic processing unit that includes a driver and a controller. The controller may be configured to run a daemon process that optimizes a shader and/or a shader pipeline for an application that is resident on the computing device when the computing device is not running the application and stores at least one optimization for the shader in the storage. The at least one optimization may be based on the application. The daemon process may further receive a request from the driver of the GPU for an optimization for the shader/shader pipeline during a runtime compilation of the shader and provide the at least one optimization to the driver of the GPU from the storage.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 3, 2022
    Inventors: Gabriel T. Dagani, Raun M. Krisch, Zachary Neyland, Robert Metzger, David C. Tannenbaum
  • Patent number: 7111292
    Abstract: An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program capable of contributing to one or more functions of the appliance. The appliance also includes a controller operable to process at least a portion of the program stored on the hidden portion of memory. The appliance further includes an external interface operable to provide access to at least an open portion of the memory. In one particular embodiment, the hidden portion of memory is inaccessible through the external interface. After modifying the at least a portion of the program, a decrypted update file is deleted from the open portion of memory and the external interface may be reestablished.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: William B. Bonnett, Gabriel T. Dagani, Alec C. Robinson
  • Publication number: 20030051090
    Abstract: An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program capable of contributing to one or more functions of the appliance. The appliance also includes a controller operable to process at least a portion of the program stored on the hidden portion of memory. The appliance further includes an external interface operable to provide access to at least an open portion of the memory. In one particular embodiment, the hidden portion of memory is inaccessible through the external interface.
    Type: Application
    Filed: July 17, 2002
    Publication date: March 13, 2003
    Inventors: William B. Bonnett, Gabriel T. Dagani, Alec C. Robinson