Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a boot operation of the data storage device is initiated, the controller retrieves a relevant boot file from the memory device to boot the data storage device with. The relevant boot file to be retrieved from a plurality of boot files may be determined by a write temperature corresponding to the temperature of when the boot file was programmed to the memory device and a read temperature of the boot file during the boot operation. Each boot file of the plurality of boot files is programmed using different programming parameters in order to cover a range of possible retention levels.

Abstract: A data storage device and method for reducing read disturbs when reading redundantly-stored data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The memory is configured to redundantly store a plurality of copies of data, wherein the plurality of copies of the data comprise a primary copy of the data and at least one secondary copy of the data. The controller is configured to randomly select one of the plurality of copies of the data instead of selecting the primary copy of the data as a default; and read, from the memory, the randomly-selected one of the plurality of copies of the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.

Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.

Abstract: A data storage device includes a non-volatile memory (NVM) device and a controller coupled to the NVM device. The controller is configured to create a bad block table that tracks bad blocks of the NVM device, send the bad block table to a host memory location, and check the bad block table to determine whether a block to be read or written to is bad. The controller is further configured to request information on a bad block from the bad block table located in the host memory location, determine that the requested information is not available from the host memory location, and retrieve the requested information from a location separate from the host memory location. A sum of the times to generate a request to check the flat relink table, execute the request, and retrieve the requested information is less than a time to process a host command.

Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.

Abstract: A data storage device includes a non-volatile memory (NVM) device and a controller coupled to the NVM device. The controller is configured to create a bad block table that tracks bad blocks of the NVM device, send the bad block table to a host memory location, and check the bad block table to determine whether a block to be read or written to is bad. The controller is further configured to request information on a bad block from the bad block table located in the host memory location, determine that the requested information is not available from the host memory location, and retrieve the requested information from a location separate from the host memory location. A sum of the times to generate a request to check the flat relink table, execute the request, and retrieve the requested information is less than a time to process a host command.

Abstract: A storage system and method for using memory allocated in a host for read data as a host memory buffer are provided. In one embodiment, a controller of a storage system receives a read request from a host for data stored in the memory, wherein the read request identifies a storage location in the host that is allocated by the host to store the requested data after it is received from the storage system. Prior to sending the requested data to the host, the storage system uses the allocated storage location in the host as a host memory buffer to store other data until the host needs the allocated storage location to store the requested data. Other embodiments are provided.

Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.

Abstract: A storage system and method for using memory allocated in a host for read data as a host memory buffer are provided. In one embodiment, a controller of a storage system receives a read request from a host for data stored in the memory, wherein the read request identifies a storage location in the host that is allocated by the host to store the requested data after it is received from the storage system. Prior to sending the requested data to the host, the storage system uses the allocated storage location in the host as a host memory buffer to store other data until the host needs the allocated storage location to store the requested data. Other embodiments are provided.

Abstract: The present disclosure generally relates to calibrating the communication with a memory device. To ensure proper calibration, interface training (IFT) needs to occur. IFT involves aligning the sampling point, which is an inflection point, of a clock signal with a data signal. The sampling point of the clock (i.e., the clock edge) needs to be located within the valid window of the data signal. The valid window of the data signal is the time in which the signal is guaranteed to be stable, i.e., after the signal has finished the signal transition time. If the sampling point is aligned with the inflection point of the data signal, then the data signal is not properly aligned. If the sampling point is aligned with the rising or falling edge of the data signal, the data may be obtained, but the data signal is misaligned and is dangerously close to being unreadable.

Abstract: Exemplary methods and apparatus are disclosed to select data evacuation policies for use by a solid state device (SSD) to relocate data from an upper (high performance) memory tier to a lower memory tier. The upper tier may be, e.g., a single-layer cell (SLC) tier of a multi-tier NAND memory, whereas the lower tier may be, e.g., a triple-layer cell (TLC) or a quad-level cell (QLC) tier of the NAND memory. In one example, the SSD monitors its recent input/output (I/O) command history. If a most recent command was a read command, the SSD performs a “lazy” evacuation procedure to evacuate data from the upper tier storage area to the lower tier storage area. Otherwise, the SSD performs a “greedy” or “eager” evacuation procedure to evacuate the data from the upper tier to the lower tier. Other evacuation selection criteria are described herein based, e.g., upon predicting upcoming I/O commands.

Abstract: A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.

Abstract: A non-volatile memory die includes a plurality of non-volatile memory cells and die control circuitry. The die control circuitry is configured to respond to a received command to access the plurality of non-volatile memory cells by sending a response indicated by the received command together with die variable information. The die variable information includes information not indicated by the received command.

Abstract: A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.

Abstract: The disclosure relates in some aspects to reporting the amount of available physical storage space of a non-volatile memory (NVM) array. A device including an NVM array may send reports regarding the amount of available physical storage space in the non-volatile memory device to a host device or some other suitable apparatus. The amount of available physical storage space takes into account whether any of the physical address blocks of the NVM array have been designated as worn-out. The host device (or other suitable apparatus) may send a report to a user when the amount of available physical storage space is relatively low.

Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.

Abstract: A non-volatile memory die includes a plurality of non-volatile memory cells and die control circuitry. The die control circuitry is configured to respond to a received command to access the plurality of non-volatile memory cells by sending a response indicated by the received command together with die variable information. The die variable information includes information not indicated by the received command.

Abstract: The disclosure relates in some aspects to reporting the amount of available physical storage space of a non-volatile memory (NVM) array. A device including an NVM array may send reports regarding the amount of available physical storage space in the non-volatile memory device to a host device or some other suitable apparatus. The amount of available physical storage space takes into account whether any of the physical address blocks of the NVM array have been designated as worn-out. The host device (or other suitable apparatus) may send a report to a user when the amount of available physical storage space is relatively low.