Abstract: Method, apparatus and product for using traces of an original model to verify a modified model. The method comprising obtaining a trace exemplifying a checker failing in a model; obtaining a modified model, wherein the modified model is a modified version of the model which was modified in an attempt to resolve the checker failing in the model; re-simulating the trace in the modified model to generate a second trace, wherein said re-simulating is performed by a processor; comparing the trace and the second trace to identify a common prefix, wherein the common prefix ends immediately before a cycle in which a state according to the trace is different than a state according to the second trace; and guiding verification of the modified model using values derived from the common prefix.

Abstract: A computer-implement method, computerized apparatus and computer program product for formal verification of an arbiter design. The method comprising: performing formal verification of an arbiter design, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; and wherein the formal verification is performed with respect to a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions.

Abstract: Method, apparatus and product for using traces of an original model to verify a modified model. The method comprising obtaining a trace exemplifying a checker failing in a model; obtaining a modified model, wherein the modified model is a modified version of the model which was modified in an attempt to resolve the checker failing in the model; re-simulating the trace in the modified model to generate a second trace, wherein said re-simulating is performed by a processor; comparing the trace and the second trace to identify a common prefix, wherein the common prefix ends immediately before a cycle in which a state according to the trace is different than a state according to the second trace; and guiding verification of the modified model using values derived from the common prefix.

Abstract: A computer-implement method, computerized apparatus and computer program product for formal verification of an arbiter design. The method comprising: performing formal verification of an arbiter design, wherein the arbiter design is based on an original arbiter design comprising a fairness logic and an arbitration logic, wherein the arbiter design comprising the arbitration logic and a portion of the fairness logic; and wherein the formal verification is performed with respect to a multi-dimensional Complete Random Sequence (CRS) having two or more dimensions.

Abstract: A reference model may be defined to refer to a matrix of a target computerized system. The reference model may comprise a reference index and a reference matrix. The reference index may have a non-deterministic value enabling the reference matrix to refer to the matrix using a fewer number of cells. The disclosed subject matter may enable a more efficient model checking process of a computerized device by using a reference model that is relatively easy to define or maintain or by using a reference model that is configured to be more efficient for model checking as it uses non-determinism.

Abstract: A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

Abstract: A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

Abstract: Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

Abstract: A reference model may be defined to refer to a matrix of a target computerized system. The reference model may comprise a reference index and a reference matrix. The reference index may have a non-deterministic value enabling the reference matrix to refer to the matrix using a fewer number of cells. The disclosed subject matter may enable a more efficient model checking process of a computerized device by using a reference model that is relatively easy to define or maintain or by using a reference model that is configured to be more efficient for model checking as it uses non-determinism.

Abstract: Methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.

Abstract: Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

Abstract: Methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.

Abstract: Methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.

Abstract: Methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.

Abstract: Methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.

Abstract: Described are methods and systems for dynamic natural language understanding. A hierarchical structure of semantic categories is exploited to assist in the natural language understanding. Optionally, the natural language to be understood includes a request.