Abstract: In an embodiment, a differential buffer includes: first and second input terminals configured to receive a differential input voltage; first and second output terminals configured to provide a differential output voltage; a differential source follower amplifier having first and second inputs respectively coupled to the first and second input terminals, and first and second outputs respectively coupled to the first and second output terminals; and a differential common source amplifier having first and second inputs respectively coupled to the second and first output terminals via a first pair of capacitors, and first and second outputs respectively coupled to the first and second output terminals.

Abstract: A circuit an amplifier stage that amplifier stage includes a positive amplifier branch and a negative amplifier branch and has current flow paths therethrough cascaded in a flow line for a core current for the amplifier stage between a supply node and a ground node. The positive and negative amplifier branches have respective input nodes configured to receive an input signal applied therebetween. A current mirror loop can be coupled to the respective input nodes of the positive and negative amplifier branches and provides an adjustable high-impedance bias source for the core current for the amplifier stage. In addition to, or instead of the current mirror loop, the circuit can include stability network having a gain bandwidth range. The amplifier stage is configured to short-circuit the output signal from the amplifier stage within the gain bandwidth range based on an output voltage setting signal.

Abstract: A circuit includes an amplifier and a feedback network coupled between the input and the output of the amplifier. The feedback network includes a plurality of parallel coupled branches, each branch having a first selection switch coupled to the input, a second selection switch coupled to the output, and an impedance between the first and second selection switches. Each branch includes a plurality of signal feedback paths coupled in parallel, each having a tuning switch coupled between the first selection switch and the second selection switch of that branch. A control unit is coupled to the feedback network and configured to vary a gain of the amplifier by selectively placing the first and second selection switches of each branch in a conductive state or a non-conductive state and selectively activating respective tuning switches of any branch having first and second selection switches in the conductive state.

Abstract: A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i?1 in the sequence.

Abstract: A receiver or transmitter circuit includes a signal propagation path between a radio-frequency (RF) signal node and a baseband processing circuit. Variable gain circuitry is configured to vary a gain applied to a signal propagating between the RF signal node and the baseband processing circuit. The variable gain circuitry varies the gain via first, coarse steps as well as via second, fine steps. This facilitates fine matching of the gains experienced by signals propagating over the in-phase and the quadrature branches in the transmitter and/or receiver circuit.

Abstract: In a method for producing a plain bearing, an aluminum-iron-silicon alloy is rolled onto a steel backing, wherein the ratio of iron to silicon is between 2:1 and 4:1. A plain bearing has a sliding surface of such an aluminum-iron-silicon alloy.

Abstract: In a method for producing a plain bearing, an aluminium-iron-silicon alloy is rolled onto a steel backing, wherein the ratio of iron to silicon is between 2:1 and 4:1. A plain bearing has a sliding surface of such an aluminium-iron-silicon alloy.

Abstract: The present invention refers to a cascode amplifier suitable for amplifying a voltage signal present on the input terminal. The amplifier comprises at least one first transistor comprising a non-drivable input terminal that coincides with the input terminal of the amplifier, a non-drivable output terminal and a drivable terminal connected to a first polarization voltage. The amplifier comprises in addition at least one second transistor comprising a non-drivable input terminal in common with the output terminal of the first transistor, an output terminal non-drivable connected to a second polarization voltage and a drivable terminal.

Abstract: The present invention refers to a cascode amplifier suitable for amplifying a voltage signal present on the input terminal. The amplifier comprises at least one first transistor comprising a non-drivable input terminal that coincides with the input terminal of the amplifier, a non-drivable output terminal and a drivable terminal connected to a first polarisation voltage. The amplifier comprises in addition at least one second transistor comprising a non-drivable input terminal in common with the output terminal of the first transistor, an output terminal non-drivable connected to a second polarisation voltage and a drivable terminal.

Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

Abstract: A current mirror circuit is provided with recovery having high output impedance. The current mirror includes a differential stage having a pair of transistors, and a voltage feedback loop which is stabilized and closed on a first one of the transistors of the differential stage. A second one of the transistors of the differential stage is connected, by its base terminal, to the collector terminal of an output transistor and, by its collector terminal, to the supply voltage. Moreover, the circuit includes a positive feedback loop which has the second transistor of the differential stage and the output transistor. A low-impedance circuit branch is connected to the base terminal of the second transistor of the differential stage and to the collector terminal of the output transistor.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations.

Abstract: A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor.

Abstract: The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.

Abstract: A temperature-compensated high-speed timing circuit, which is particularly advantageous in read-interface circuits for disk-drive interface. The voltage on the integrating capacitor is compared against a voltage defined by the drop, on a resistor, induced by a current which is the combination of a reference current from a reference current generator with a temperature-dependent current from another current generator.

Abstract: A current generator stage for integrated analog circuits includes a current source connected between a supply voltage and a ground terminal. A current mirror is operationally connected to the current source to generate an output current. A bias circuit is operationally connected to the current source to perform switching of the current source from a first operating mode to a second operating mode. The bias circuit includes an energy storage circuit which, in a first circuit configuration, supplies to the current source a first predetermined voltage when the current source is in the first operating mode. The energy storage circuit in a second circuit configuration is a combination of first and second reactances to supply to the current source a second predetermined voltage when the current source is in the second operating mode.

Abstract: A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision.

Abstract: An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.