Patents by Inventor Gaius Gillman Fountain
Gaius Gillman Fountain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978681Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers.Type: GrantFiled: May 26, 2022Date of Patent: May 7, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
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Patent number: 11967575Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.Type: GrantFiled: February 25, 2022Date of Patent: April 23, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Guilian Gao, Javier A. DeLaCruz, Shaowu Huang, Liang Wang, Gaius Gillman Fountain, Jr., Rajesh Katkar, Cyprian Emeka Uzoh
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Patent number: 11955393Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.Type: GrantFiled: May 7, 2021Date of Patent: April 9, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Rajesh Katkar, Laura Wills Mirkarimi, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh
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Patent number: 11955445Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.Type: GrantFiled: June 9, 2022Date of Patent: April 9, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Belgacem Haba, Rajesh Katkar
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Patent number: 11955463Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.Type: GrantFiled: February 25, 2022Date of Patent: April 9, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
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Publication number: 20240088101Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.Type: ApplicationFiled: August 17, 2023Publication date: March 14, 2024Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, JR., Cyprian Emeka Uzoh, Belgacem Haba, Laura Wills Mirkarimi, Rajesh Katkar
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Publication number: 20240047344Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: ApplicationFiled: August 17, 2023Publication date: February 8, 2024Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
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Patent number: 11855064Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.Type: GrantFiled: June 10, 2021Date of Patent: December 26, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Guilian Gao, Gaius Gillman Fountain, Jr.
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Publication number: 20230352369Abstract: Embodiments herein include post-TSV reveal processing methods and devices formed using the methods. In some embodiments, the methods include forming an electrically and thermally conductive layer on the device that may be used as a power/ground connection path or a thermal spreading plane in a device assembly that includes a plurality of interconnected stacked devices.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Gaius Gillman Fountain, JR., George Carlton Hudson
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Patent number: 11791307Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.Type: GrantFiled: March 23, 2021Date of Patent: October 17, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Chandrasekhar Mandalapu, Gaius Gillman Fountain, Jr., Guilian Gao
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Patent number: 11756880Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: GrantFiled: September 27, 2021Date of Patent: September 12, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
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Publication number: 20230282610Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.Type: ApplicationFiled: December 29, 2022Publication date: September 7, 2023Inventors: Cyprian Emeka Uzoh, Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, JR.
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Patent number: 11749645Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.Type: GrantFiled: June 12, 2019Date of Patent: September 5, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Belgacem Haba, Laura Wills Mirkarimi, Rajesh Katkar
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Publication number: 20230268308Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.Type: ApplicationFiled: December 16, 2022Publication date: August 24, 2023Inventors: Gaius Gillman Fountain, JR., Chandrasekhar Mandalapu, Cyprian Emeka Uzoh, Jeremy Alfred Theil
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Publication number: 20230268300Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.Type: ApplicationFiled: February 23, 2023Publication date: August 24, 2023Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Gaius Gillman Fountain, Jr., Guilian Gao, Jeremy Alfred Theil, Gabriel Z. Guevara, Kyong-Mo Bang, Laura Wills Mirkarimi
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Publication number: 20230253383Abstract: Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Gaius Gillman Fountain, JR., Chandrasekhar Mandalapu, Laura Wills Mirkarimi
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Publication number: 20230207322Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.Type: ApplicationFiled: December 28, 2022Publication date: June 29, 2023Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR.
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Publication number: 20230207474Abstract: A bonded structure comprising a first semiconductor element, a second semiconductor element spaced apart from the first semiconductor element by a gap, and an interconnect assembly comprising an insulating substrate with conductive traces, the insulating substrate including a first section directly bonded to the first semiconductor element, a second section directly bonded to the second semiconductor element, and a flexible section disposed between the first and second sections, the flexible section at least partially bridging the gap.Type: ApplicationFiled: December 22, 2022Publication date: June 29, 2023Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Thomas Workman, Belgacem Haba, Rajesh Katkar, Laura Wills Mirkarimi
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Publication number: 20230207514Abstract: A system for direct bonding can include a substrate support configured to hold a substrate for direct bonding and a die handling tool including an end effector configured to hold a die and bring the die into contact with the substrate supported on the substrate support, the end effector configured to initiate contact between the substrate and a bond initiation region of the die and to subsequently allow contact between the substrate and other regions of the die.Type: ApplicationFiled: December 21, 2022Publication date: June 29, 2023Inventors: Guilian Gao, Gaius Gillman Fountain, JR., Cyprian Emeka Uzoh, Thomas Workman
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Publication number: 20230207402Abstract: A bonded structure comprises a frame element having a cavity formed through its thickness. The frame element is directly bonded to a first element at a first side and to a second element at a second side enclosing the cavity. The frame element may comprise a through substrate via (TSV). Redundant conductive contact pads may be formed in bonding layers for enhanced direct bonding quality and reliability.Type: ApplicationFiled: December 23, 2022Publication date: June 29, 2023Inventors: Gaius Gillman Fountain, JR., Guilian Gao, George Carlton Hudson, Laura Wills Mirkarimi