Abstract: Disclosed herein are systems and methods for performing angled confocal spectroscopy. Angled confocal spectroscopy permits sensitive, non-invasive investigation of numerous analytes in a wide variety of samples, including tissues and bodily fluids. The methods and systems disclosed herein can be used to measure spectroscopic signatures of analytes within well-defined and very small regions of samples, while at the same time achieving superior rejection of signal contributions from analytes within the sample that do not fall within a volume of interest. Accordingly, measurements can be performed at comparatively high signal-to-noise ratios, and can provide information such as concentrations and distributions of sample analytes at high spatial resolution. By using cylindrically-focused illumination light, samples can be excited by a “sheet” of light, allowing spatial signal averaging and enhancing the stability and reproducibility of the measurements.

Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.

Abstract: A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

Abstract: A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage.

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.

Abstract: A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the critical path. This optimizes the multiplexor and functional flip-flop orientation, allowing for a significant reduction in the time required from output of the functional flip-flop to a pin or to the interior of the CPU (the clock to q delay). In order to ensure that boundary scan mode functions properly, the functional flip-flop may be designed to act as a buffer, i.e. become transparent, when the boundary scan cell is in boundary scan mode.

Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.

Abstract: A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure.

Abstract: An integrated circuit device for synchronization of data in a data path includes a driver and a storage element coupled to the driver for driving the storage element. The storage element is coupled to the data path outside the data path. The integrated circuit employs a method of operation including passing a time pulse, sampling data during the time pulse, passing the data to a computation logic along a data path, and storing the sampled data in a storage element connected to but outside the data path.

Abstract: A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.

Abstract: The present invention is directed to an apparatus and method to clamp and terminate signals along a communication bus; the clamping and termination are performed dynamically whenever a signal exceeds a set peak value or falls below a set low value. Variations include a clamping and termination circuit made of metal oxide semiconductor (MOS) devices where one MOS device clamps for over-voltage and another MOS device clamps for under-voltage. Biasing circuits to the gates of the MOS devices assure that proper bias voltage is applied so that the MOS devices only clamp and terminate when a signal is received and that signal falls off the set high or low values, this assures dynamic clamping and termination and avoids unnecessary additional voltage from a driving device.

Abstract: Methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions. The circuit detects the level of the signal at an external terminal and adjusts the voltage at the gate terminals of the output transistors connecting to the external terminal in response thereto, such that oxide stress conditions are alleviated.

Abstract: Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and reliably detect input logic signals in the presence of overshoot or undershoot conditions. In a preferred embodiment, the source terminals of input transistors are biased such that the impact of overshooting or undershooting signals at the input terminal are drastically reduced.

Abstract: An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels is disclosed. The present invention uses various circuit techniques to ensure that no transistor in the input buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the input signal voltage may swing well beyond the tolerable voltage levels. This is accomplished without compromising the reliability of the input buffer circuit in detecting the logic levels of the input signal.

Abstract: A circuit which can compensate for process variations in controlling a drive transistor, whether for driving internal circuits or an output driver. A drive circuit is connected to the gate of the drive transistor, and is controlled by a control logic signal. In response to the control logic signal transitioning, the drive circuit will drive the gate to a voltage which is set depending upon the amount of process variation.

Abstract: A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount.

Abstract: A voltage bias generator circuit which uses a series of small transistors to form essentially a resistor ladder to produce a desired bias voltage at an intermediate node using the sizing of the transistors and the placement of the node. The output node is then connected to a first voltage level shifting circuit for shifting the voltage by at least 1 V.sub.T. The output of the first voltage level shifting circuit is then coupled to the second voltage level shifting circuit, which shifts it back down or up to the desired bias voltage.

Abstract: Various methods and circuitry for implementing output buffers with low voltage CMOS transistors capable of handling signal overshoot and undershoot conditions at an external terminal are disclosed. The present invention detects the level of the signal at the external terminal and adjusts the voltage at the gate terminals of the output transistors connecting to the external terminal in response thereto, such that oxide stress conditions are alleviated. In one embodiment, dynamic biasing techniques are developed by the present invention to ensure that the circuitry protecting the output devices is itself protected against voltage stress caused by overshoot and undershoot at the external terminal.

Abstract: A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount. The pull-down circuit is a transistor connected to a low voltage source, which limits the pull-down voltage. Additional transistors are provided to turn on and off the pull-down transistor, with a circuit connected to a fail-safe low voltage source being used to protect these transistors.