Abstract: Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic de-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.

Abstract: Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.

Abstract: The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.

Abstract: Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.

Abstract: The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.

Abstract: Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.

Abstract: Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic dc-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.

Abstract: The invention relates to an apparatus and a method for glitch-free clock switching. In one embodiment this is accomplished by a first clock source, one or more second clock source and a clock switching control device configured to synchronize the receive input clock from the first clock source and the second clock source, and output at least one of the them according to control signal selection.

Abstract: Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.