Abstract: A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if th

Abstract: A method of monitoring messages from a sensor using an integrated circuit is provided. The messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit. The interconnect circuitry connects the sensor to one or more core devices configured to process the messages. A first hash value is calculated for the first message. The first hash value is compared to one or more prior hash values stored in a hash store. Each prior hash value of the one or more prior hash values corresponds to a message that was read from the interconnect circuitry prior to the first message. A corrective action is performed when a difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.

Abstract: A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if th

Abstract: A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.

Abstract: An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action.

Abstract: An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action.

Abstract: A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

Abstract: A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

Abstract: An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

Abstract: A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.