Patents by Inventor Ganesh Upadhyaya
Ganesh Upadhyaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230320062Abstract: A substrate processing system includes a memory that stores a recipe of an electrical coupling process for electrical coupling a capacitor to an active silicon region of a memory structure. A system controller, according to the recipe, implements the at least a portion of the electrical coupling process including: performing deposition and etch cycles to remove a portion of one or more dielectric layers from a substrate, enlarge a trench between adjacent bitline structures of the memory structure, and provide access to a polymer layer or a dielectric layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to provide access for electrically coupling the capacitor to the active silicon region.Type: ApplicationFiled: March 16, 2022Publication date: October 5, 2023Inventors: Ratndeep SRIVASTAVA, Hui GAO, Samantha DOAN, Ganesh UPADHYAYA, Gowri Channa KAMARTHY
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Patent number: 11211253Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.Type: GrantFiled: June 25, 2020Date of Patent: December 28, 2021Assignee: Lam Research CorportationInventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
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Patent number: 11170997Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.Type: GrantFiled: April 10, 2020Date of Patent: November 9, 2021Assignee: Lam Research CorporationInventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
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Publication number: 20200328087Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
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Patent number: 10734238Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.Type: GrantFiled: November 21, 2017Date of Patent: August 4, 2020Assignee: Lam Research CorporationInventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
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Publication number: 20200243326Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
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Patent number: 10658174Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.Type: GrantFiled: November 21, 2017Date of Patent: May 19, 2020Assignee: Lam Research CorporationInventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
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Patent number: 10515815Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.Type: GrantFiled: November 21, 2017Date of Patent: December 24, 2019Assignee: Lam Research CorporationInventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun
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Publication number: 20190157066Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
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Publication number: 20190157096Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Inventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun
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Publication number: 20190157095Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
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Patent number: 9466466Abstract: Methods, systems, and computer programs are presented for optimizing Critical Dimension Uniformity (CDU) during the processing of a substrate. One method includes identifying an operation of a recipe for processing a substrate within a chamber, the operation being configured to provide a pulsed radio frequency (RF) to the chamber. A plurality of tests are performed in the chamber for the operation utilizing the pulsed RF, each test having a duty cycle for the pulsed RF selected from a plurality of RF duty cycles. The method also includes for each test, measuring the critical dimension (CD) and the CDU for features in the substrate, and selecting a first duty cycle from the plurality of RF duty cycles based on the measured CDs and CDUs for the plurality of tests. The method also includes setting the selected first duty cycle in the operation of the recipe for processing the substrate.Type: GrantFiled: September 14, 2015Date of Patent: October 11, 2016Assignee: Lam Research CorporationInventors: Qinghua Zhong, Ryan Martin, Ganesh Upadhyaya
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Patent number: 9385003Abstract: Systems and methods for etching a substrate include arranging a substrate including a first structure and a dummy structure in a processing chamber. The first structure is made of a material selected from a group consisting of silicon dioxide and silicon nitride. The dummy structure is made of silicon. Carrier gas is supplied to the processing chamber. Nitrogen trifluoride and molecular hydrogen gas are supplied to the processing chamber. Plasma is generated in the processing chamber. The dummy structure is etched.Type: GrantFiled: February 16, 2015Date of Patent: July 5, 2016Assignee: LAM RESEARCH CORPORATIONInventors: Ming-Shu Kuo, Qinghua Zhong, Helene Del Puppo, Ganesh Upadhyaya, Gowri Kamarthy
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Publication number: 20160049495Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.Type: ApplicationFiled: August 18, 2014Publication date: February 18, 2016Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
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Patent number: 9252238Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.Type: GrantFiled: August 18, 2014Date of Patent: February 2, 2016Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
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Patent number: 8431461Abstract: A method for forming devices with silicon gates over a substrate is provided. Silicon nitride spacers are formed on sides of the silicon gates. An ion implant is provided using the silicon nitride spacers as masks to form ion implant regions. A nonconformal layer is selectively deposited over the spacers and gates that selectively deposits a thicker layer on tops of the gates and spacers and between spacers than on sidewalls of the silicon nitride spacers. Sidewalls of the nonconformal layer are etched away on sidewalls of the silicon nitride spacers. The silicon nitride spacers are trimmed.Type: GrantFiled: December 16, 2011Date of Patent: April 30, 2013Assignee: Lam Research CorporationInventors: Qinghua Zhong, Yoshie Kimura, Tae Won Kim, Qian Fu, Gladys Lo, Ganesh Upadhyaya, Yoko Yamaguchi