Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: In accordance with an embodiment, a semiconductor package includes a first surface configured to be mounted on a circuit board, and a region of thermally expandable material configured to push the first surface of the semiconductor package away from the circuit board when a temperature of the thermally expandable material exceeds a first temperature.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer.

Abstract: In an improved method for bumped wafer thinning, a wafer is provided having a front side and a back side wherein contact pads are formed on the top surface. A dry film is formed on the front side of the wafer and openings are provided in the dry film to the contact pads. Interconnections, such as solder bumps, are formed within the openings on the contact pads. A back grind tape or carrier is attached to the dry film and overlying the interconnections. Thereafter, the wafer is thinned from the back side of the wafer.