Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.

Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.

Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.

Abstract: A display device includes a display array and a driving circuit. The display array includes at least one scan line. The driving circuit drives the display array and includes a timing controller and a gate driver. The timing controller controls a refresh rate of the display array at a first frequency or a second frequency, where the first frequency is higher substantially than the second frequency. The gate driver switches between supplying an enable voltage signal and a disable voltage signal to the scan line. Under the first or frequency, a corresponding first or second voltage difference exists between the enable voltage signal and the disable voltage signal. The first voltage difference is substantially greater than the second voltage difference, and the enable voltage signal has a same enable period.

Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

Abstract: A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

Abstract: A pixel structure includes a scan line, a signal line and a first pixel. The first pixel includes a switch device and a pixel electrode. A gate of the switch device is electrically connected to the scan line. The pixel electrode is electrically connected to the switch device, and the pixel electrode includes a plurality of slits. The signal line includes a first portion and a second portion, the pixel electrode overlaps the first portion of the signal line, and the scan line overlaps the second portion of the signal line. The first portion of the signal line includes at least one bent portion, the bent portion is disposed along the arrangement directions of the slits, and the pixel electrode covers the edges of the bent portion of the signal line.

Abstract: A pixel structure includes a scan line, a signal line and a first pixel. The first pixel includes a switch device and a pixel electrode. A gate of the switch device is electrically connected to the scan line. The pixel electrode is electrically connected to the switch device, and the pixel electrode includes a plurality of slits. The signal line includes a first portion and a second portion, the pixel electrode overlaps the first portion of the signal line, and the scan line overlaps the second portion of the signal line. The first portion of the signal line includes at least one bent portion, the bent portion is disposed along the arrangement directions of the slits, and the pixel electrode covers the edges of the bent portion of the signal line.

Abstract: A display device includes a display array and a driving circuit. The display array includes at least one scan line. The driving circuit drives the display array and includes a timing controller and a gate driver. The timing controller controls a refresh rate of the display array at a first frequency or a second frequency, where the first frequency is higher substantially than the second frequency. The gate driver switches between supplying an enable voltage signal and a disable voltage signal to the scan line. Under the first or frequency, a corresponding first or second voltage difference exists between the enable voltage signal and the disable voltage signal. The first voltage difference is substantially greater than the second voltage difference, and the enable voltage signal has a same enable period.

Abstract: An array substrate includes a plurality of pixel regions and a plurality of pixel electrodes. Each pixel region includes a first sub-pixel region and a second sub-pixel region. Each pixel electrode includes a first electrode disposed in the first sub-pixel region and a second electrode disposed in the second sub-pixel region. The first electrode includes a first main electrode dividing the first sub-pixel region into a first alignment region and a second alignment region. The second electrode includes a second main electrode dividing the second sub-pixel region into a third alignment region and a fourth alignment region. The first, the second, the third, and the fourth alignment regions are sequentially arranged in a first direction. The first electrode and the second electrode are separated by a gap, and a width of the gap in the first direction is less than a width of one of the first, the second, the third, and the fourth alignment regions in the first direction.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: A photosensitive pixel circuit of a touch module including an output transistor and a light detection unit is provided. The output transistor receives a reference signal and provides a touch voltage controlled by a light detection voltage. The light detection unit is electrically connected to the output transistor, and receives a touch scan signal. The light detection unit detects an intensity of a light according to the touch scan signal so as to correspondingly provide the light detection voltage.