Patents by Inventor Gangadhara S. Mathad
Gangadhara S. Mathad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7144769Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: GrantFiled: July 27, 2004Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Patent number: 6842235Abstract: There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.Type: GrantFiled: September 28, 2001Date of Patent: January 11, 2005Assignee: Infineon Technologies North America Corp.Inventors: Syed Shoaib Hasan Zaidi, Gangadhara S. Mathad
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Patent number: 6821864Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: GrantFiled: March 7, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Patent number: 6809005Abstract: The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: GrantFiled: March 12, 2003Date of Patent: October 26, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Publication number: 20040180510Abstract: The present invention provides methods of producing trench structures having substantially void-free filler materials therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Patent number: 6743727Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.Type: GrantFiled: June 5, 2001Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Gangadhara S. Mathad, Siddhartha Panda, Rajiv M. Ranade
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Patent number: 6709917Abstract: A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.Type: GrantFiled: May 13, 2002Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Siddhartha Panda, Rajiv M. Ranade, Gangadhara S. Mathad
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Patent number: 6687014Abstract: A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.Type: GrantFiled: January 16, 2002Date of Patent: February 3, 2004Assignee: Infineon Technologies AGInventors: Shoaib Hasan Zaidi, Gangadhara S. Mathad
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Publication number: 20030170951Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: ApplicationFiled: March 7, 2002Publication date: September 11, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Subhash B. Kulkarni, Gangadhara S. Mathad, Rajiv M. Ranade
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Publication number: 20030133127Abstract: A method of measuring the rate of etching of trenches on a substrate using interferometry is provided. The method comprises transmitting onto the substrate incident electromagnetic radiation having a wavelength above the wavelength at which the trenches act as waveguides for the radiation; collecting reflected electromagnetic radiation from the substrate; detecting a repetitive pattern of maximum intensities and minimum intensities of the reflected electromagnetic radiation during the etching; and determining the rate of etching based upon the wavelength of the incident electromagnetic radiation and the time period of the pattern.Type: ApplicationFiled: January 16, 2002Publication date: July 17, 2003Inventors: Shoaib Hasan Zaidi, Gangadhara S. Mathad
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Patent number: 6544838Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.Type: GrantFiled: March 13, 2001Date of Patent: April 8, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rajiv Ranade, Munir D. Naeem, Gangadhara S. Mathad
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Publication number: 20030063272Abstract: There is provided a method for measuring planarized features on a wafer of a semiconductor device. The planarized features on the wafer are illuminated. A reflected light beam with respect to the planarized features is detected. Optical characteristics of the reflected light beam are analyzed to determine information corresponding to the planarized features. Preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a simplified geometry of the planarized features with respect to a geometry of similar, un-planarized features. Moreover, preferably, the analyzing step maximizes an analysis of the optical characteristics based upon a reduction in complexity of the planarized features due to a similarity in refractive indexes corresponding to a bulk silicon substrate and a poly silicon fill of the semiconductor device.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Syed Shoaib Hasan Zaidi, Gangadhara S. Mathad
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Publication number: 20020179570Abstract: A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gangadhara S. Mathad, Siddhartha Panda, Rajiv M. Ranade
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Patent number: 6489249Abstract: In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of tType: GrantFiled: June 20, 2000Date of Patent: December 3, 2002Assignee: Infineon Technologies AGInventors: Gangadhara S. Mathad, Rajiv Ranade
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Publication number: 20020132422Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.Type: ApplicationFiled: March 13, 2001Publication date: September 19, 2002Applicant: Infineon Technologies North America Corp.Inventors: Rajiv Ranade, Munir D. Naeem, Gangadhara S. Mathad
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Patent number: 6284666Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid.Type: GrantFiled: May 31, 2000Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Munir D. Naeem, Gangadhara S. Mathad, Byeong Yeol Kim, Stephan P. Kudelka, Brian S. Lee, Heon Lee, Elizabeth Morales, Young-Jin Park, Rajiv M. Ranade
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Patent number: 5391510Abstract: A sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions. The source/drain regions are formed by ion implantation using the expendable structure (diamond-like-carbon) as a mask. After the expendable structure has performed its further purpose of protecting the gate dielectric from contamination during the annealing cycle, the structure is easily removed by O.sub.2 plasma and replaced by a conventional metal gate material.Type: GrantFiled: April 7, 1994Date of Patent: February 21, 1995Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Gangadhara S. Mathad, Rajiv V. Joshi
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Patent number: 5258264Abstract: A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygenplasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrroldone (NMP).Type: GrantFiled: August 6, 1992Date of Patent: November 2, 1993Assignee: International Business Machines CorporationInventors: Gangadhara S. Mathad, David Stanasolovich, Giorgio G. Via
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Patent number: 5024896Abstract: A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygen plasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrrolidone (NMP).Type: GrantFiled: July 6, 1989Date of Patent: June 18, 1991Assignee: International Business Machines CorporationInventors: Gangadhara S. Mathad, David Stanasolovich, Giorgio G. Via
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Patent number: 4741799Abstract: A method of high rate anisotropic etching of silicon in a high pressure plasma is described. In one embodiment the etching ambient is a mixture of either NF.sub.3 or SF.sub.6, an inert gas such as nitrogen, and a polymerizing gas such as CHF.sub.3 that creates conditions necessary for anisotropy not normally possible with nonpolymerizing fluorinated gases in a high pressure regime. The etch process is characterized by high etch rates and good uniformity utilizing photoresist or similar materials as a mask. The present process may advantageously be used to etch deep trenches in silicon using a photoresist mask.Type: GrantFiled: November 17, 1986Date of Patent: May 3, 1988Assignee: International Business Machines CorporationInventors: Lee Chen, Gangadhara S. Mathad