Patents by Inventor Garry W. Amann
Garry W. Amann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8520009Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 29, 2009Date of Patent: August 27, 2013Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 7876378Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 14, 2007Date of Patent: January 25, 2011Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 7760209Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.Type: GrantFiled: December 17, 2007Date of Patent: July 20, 2010Assignee: NVIDIA CorporationInventors: Garry W. Amann, Stephen Lew, Sanford S. Lum
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Patent number: 7733419Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 14, 2007Date of Patent: June 8, 2010Assignee: Nvidia CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 7705915Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 14, 2007Date of Patent: April 27, 2010Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 7619687Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: December 14, 2007Date of Patent: November 17, 2009Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Patent number: 7511714Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.Type: GrantFiled: November 10, 2003Date of Patent: March 31, 2009Assignee: NVIDIA CorporationInventors: Garry W. Amann, Stephen Lew, Sanford S. Lum
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Patent number: 7508448Abstract: Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.Type: GrantFiled: May 29, 2003Date of Patent: March 24, 2009Assignee: NVIDIA CorporationInventors: Stephen D. Lew, Garry W. Amann, Hassane S. Azar
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Publication number: 20080122860Abstract: Video conversion using a 3D graphics pipeline of a graphical processing unit (GPU) is disclosed. A plurality of video data formatted in a first video format is accessed from a memory unit. Moreover, the plurality of video data is converted from the first video format to a second video format using a 3D graphics pipeline of the GPU. The plurality of video data formatted in the second video format is sent to the memory unit. The 3D graphics pipeline applies a filtering technique. In an embodiment, the filtering technique is an interpolation technique.Type: ApplicationFiled: December 17, 2007Publication date: May 29, 2008Inventors: Garry W. Amann, Stephen Lew, Sanford S. Lum
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Patent number: 7173635Abstract: Methods, apparatus and systems for the display, on a remote node, of a three-dimensional (3D) image rendered on a host system in a first image format are described. In general, the 3D image is transformed into a second image format that is compressed (i.e., uses fewer data bits per pixel) relative to the first image format, (optionally) scaled to a screen size of remote node, and subsequently transferred to remote node for display. In instances, the transformation of the image from the first image format to the second image format and the optional scaling of the image to the screen size of remote node may be done in a graphics processing unit (GPU) on the host system. As an example, the first image format may be an RGB-based format, such as RGBA (32-bits per pixel) or standard RGB (24-bits per pixel) and the second image format may be a YUV-based format, such as YV12 (12-bits per pixel).Type: GrantFiled: March 25, 2003Date of Patent: February 6, 2007Assignee: NVIDIA CorporationInventors: Garry W. Amann, Hassane S. Azar
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Publication number: 20040189677Abstract: Methods, apparatus and systems for the display, on a remote node, of a three-dimensional (3D) image rendered on a host system in a first image format are described. In general, the 3D image is transformed into a second image format that is compressed (i.e., uses fewer data bits per pixel) relative to the first image format, (optionally) scaled to a screen size of remote node, and subsequently transferred to remote node for display. In instances, the transformation of the image from the first image format to the second image format and the optional scaling of the image to the screen size of remote node may be done in a graphics processing unit (GPU) on the host system. As an example, the first image format may be an RGB-based format, such as RGBA (32-bits per pixel) or standard RGB (24-bits per pixel) and the second image format may be a YUV-based format, such as YV12 (12-bits per pixel).Type: ApplicationFiled: March 25, 2003Publication date: September 30, 2004Applicant: NVIDIA CorporationInventors: Garry W. Amann, Hassane S. Azar