Abstract: A computer system includes multiple memory arrays, each potentially as large as the maximum number of locations for which the associated processor can generate unique addresses. During the processing of such instructions a memory array selection mechanism permits data to be read from or written into any of the memory arrays. Program control may be transferred from an instruction in one memory array to an instruction in another memory array. In addition, memory references may be made to more than one memory array.

Abstract: A central processing unit wherein instruction fetch and execution is performed by a mechanism featuring an instruction look ahead mechanism whereby fetching and processing of the next software instruction is commenced as a last step of the currently executing software instruction, and the currently executing software instruction is terminated by the first portion of the next software instruction.

Abstract: A dispatcher mechanism for assigning to a processor the highest priority peripheral having the highest priority request. In a data processing system having at least one processor, and a plurality of peripheral devices coupled to a system interface unit SIU utilized for communication between said processor and peripheral devices, and also having a plurality of processes competing for control of said processor, a priority interrupt mechanism determines the highest priority peripheral having the highest priority request and then provides an interrupt signal to the processor. A release instruction REL is used to exit the process. The dispatcher mechanism dispatches data to the processor upon request from the processor in order to give control of the processor to the highest priority request.

Abstract: Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.