Abstract: A component group table in a receiving node of a computer network stores access permission information for enabling the receiving node to validate an access request issued by a requesting node. An incoming access request at a receiving node includes a subnet ID/component ID (“SID/CID”) tuple. The receiving node selectively computes a component group table address for the requesting node according to an address mapping function determined by the value of at least one predetermined bit within the SID/CID tuple of the incoming access request. Using at least one bit in the SID/CID tuple enables the establishment of at least two address mapping regions in the component group table, such as separate regions for storage nodes and compute nodes in the network.

Abstract: A component group table in a receiving node of a computer network stores access permission information for enabling the receiving node to validate an access request issued by a requesting node. An incoming access request at a receiving node includes a subnet ID/component ID (“SID/CID”) tuple. The receiving node selectively computes a component group table address for the requesting node according to an address mapping function determined by the value of at least one predetermined bit within the SID/CID tuple of the incoming access request. Using at least one bit in the SID/CID tuple enables the establishment of at least two address mapping regions in the component group table, such as separate regions for storage nodes and compute nodes in the network.

Abstract: A method and apparatus determine which of a plurality of queue buffers (26, 126, 426) contains a complete packet and transmit a de-queue signal to one of the plurality of queue buffers (26, 126, 426) determined to contain a complete packet.

Abstract: A lossy fabric transmitting device includes a queue, a link transmitter to transmit packets from the queue, a trigger mechanism to automatically discard a packet contained in the queue in response to satisfaction of a packet dropping threshold and a discard counter to track packets being discarded from the queue. The discard counter has a failure detection threshold. The discard counter resets in response to the link transmitter transmitting a packet. Satisfaction of the failure detection threshold identifies the link transmitter as being immediately adjacent a failed link of a lossy fabric.

Abstract: A method and apparatus determine which of a plurality of queue buffers (26, 126, 426) contains a complete packet and transmit a de-queue signal to one of the plurality of queue buffers (26, 126, 426) determined to contain a complete packet.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.

Abstract: A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X?1)/2], wherein X equals the number of processor clusters.

Abstract: A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.

Abstract: Disclosed are systems and methods providing a unified system fabric in a computer. The systems and methods of embodiments including first interface disposed between a first component of the computer system and a second component of the computer system, the first interface implementing an interface protocol, and a second interface disposed between the first component of the computer system and a third component of the computer system, the second interface implementing the interface protocol, wherein the first interface and the second interface comprise separate signal paths at the first component.

Abstract: A controller arrangement and method for effectuating data transfer between a first clock domain and a second clock domain. In one embodiment, inversion circuitry inverts a first clock signal associated with the first clock domain into an inverted first clock signal that is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain. Clock synchronizer controller circuitry operates responsive to sampled sync pulses based on the SYNC pulse to generate domain synchronizer control signals for effectuating data transfer between the first and second clock domains.

Abstract: In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.

Abstract: An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device.

Abstract: A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from a second type of device that uses a second cache-line size, such that communications between the first type of devices are enabled over a plurality of first routes, such that communications between the second type of devices are enabled over a plurality of second routes, and such that communications between the first type of devices and the second type of devices are disabled.

Abstract: An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device.

Abstract: In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.

Abstract: An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device.

Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.

Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.