Abstract: An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability.

Abstract: An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC.

Abstract: An improvement to a seismic system, which provides data words, having digital signals corresponding to sensed vibrations in an earth formation or to noise occurring in a seismic system, permits the determination of the signal to noise ratio of the seismic system in the field. The improvement comprises a new word register receiving the data word signals from the seismic system, an H register and an L register. The improvement also includes control circuits and comparators whereby the comparators and the registers are controlled so that the data word is periodically entered into a new word register and the signals provided by the new word register is compared with signals provided by the H register and the L register so that after one cycle of operation, the most positive data word occurring during the cycle is stored in either the H or L register while the most negative data word occurring is stored in the remaining register of the H and L registers.