Patents by Inventor Gary Dashney

Gary Dashney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8895430
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: November 25, 2014
    Assignee: Great Wall Semiconductor Corporation
    Inventors: Samuel J. Anderson, Gary Dashney, David N. Okada
  • Publication number: 20120248601
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, Gary Dashney, David N. Okada
  • Publication number: 20120205740
    Abstract: A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 16, 2012
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, David N. Okada, Gary Dashney, David A. Shumate
  • Publication number: 20110140200
    Abstract: A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.
    Type: Application
    Filed: December 24, 2010
    Publication date: June 16, 2011
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, David N. Okada, Gary Dashney, David A. Shumate
  • Publication number: 20090321784
    Abstract: A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 31, 2009
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, David N. Okada, David A. Shumate, Gary Dashney
  • Publication number: 20090014791
    Abstract: A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: GREAT WALL SEMICONDUCTOR CORPORATION
    Inventors: Samuel J. Anderson, David N. Okada, Gary Dashney, David A. Shumate