Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: A system and method for communicating the current congestion state of a destination virtual output queue to a plurality of source queues in order to allow the source queues to adjust their data rates in real time for each class of service is disclosed. The preferred embodiment method comprises tracking the amount of data for one or more classes of service entering and leaving at least one destination queue associated with an output port; determining the amount of available space in the destination queue; creating a message based at least in part on the determined amount of available space; and transmitting the created message to a plurality of source queues at least one of which is providing data to the destination queue.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise describing a digital signal for passing from the first set of circuitry to the second set of circuitry and detecting (230) transitions of the digital signal with respect to a timing constraint (240) of at least a portion of the second set of circuitry. Lastly, the steps comprise, responsive to detecting metastability with respect to timing of a transition of the digital signal relative to the timing constraint of at least a portion of the second set of circuitry, forcing (160) the digital signal to a random value and passing the random value to the second set of circuitry.

Abstract: An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write shift register (SRWT) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SRRD) for storing a sequence of bits.

Abstract: An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises a shift register (SRRD; SRWT) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/R1 times the integer M. The device further comprises circuitry (16) for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.

Abstract: The invention includes an automated method for instantiation of a plurality of registers within an integrated circuit or integrated circuit device, including the computer-implemented steps of defining a programming language having a plurality of keywords identified with the plurality of registers, creating a control file describing the plurality of registers using the defined programming language, providing a compiling program compatible with the control file, and executing the compiling program to generate from the control file a first set of synthesizable codes containing information on traits of each of the registers. Preferably, the synthesizable codes include RTL codes. In a further embodiment, the invention includes executing the compiler program for generating an address decoder module operative n conjunction with the first set of synthesizable code through a top-level module for instantiation of the address decoder module and the plurality of registers.

Abstract: A system includes a communication device that includes a number of interface cards and a switching complex. Upon receiving a data signal, an input card modifies header bits of the data signal to identify an input port on which the data signal was received. The switching complex uses the modified header bits to communicate the data signal to an output card and associated output port. In a particular embodiment, the switching complex may also modify header bits to identify the input card.

Abstract: A system and method for maximum utilization of bandwidth of a resource incrementally adjusts in real time the allocated bandwidth per source queue per class of service based at least in part on the current status of a destination virtual output queue fill level. By varying the permissible bandwidth incrementally not only is the available bandwidth utilized optimally but also a desired class of service is maintained.

Abstract: The invention includes an automated method for instantiation of a plurality of registers within an integrated circuit or integrated circuit device, including the computer-implemented steps of defining a programming language having a plurality of keywords identified with the plurality of registers, creating a control file describing the plurality of registers using the defined programming language, providing a compiling program compatible with the control file, and executing the compiling program to generate from the control file a first set of synthesizable codes containing information on traits of each of the registers. Preferably, the synthesizable codes include RTL codes. In a further embodiment, the invention includes executing the compiler program for generating an address decoder module operative n conjunction with the first set of synthesizable code through a top-level module for instantiation of the address decoder module and the plurality of registers.

Abstract: A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master.

Abstract: Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.