Abstract: A system for testing both simulated and real versions of an integrated circuit (IC) includes an IC simulator, a simulator manager, an IC tester, and a tester manager. The IC simulator simulates response of the IC to a set of simulated IC input signals by producing a set of simulated IC output signals. The simulator manager, programmed by a user-supplied test bench file, provides the simulated IC input signals to the simulator during the simulation. During the simulation, the simulator manager also generates a set of waveform data sequences, each representing periodically sampled values of a corresponding one of the simulated IC input and output signals. The IC tester includes a separate channel corresponding to each real IC input and output signal. The tester manager converts the waveform data sequence corresponding to each simulated IC input and output signal to a separate set of instructions provided as input to a corresponding one of the IC tester channels.

Abstract: An asynchronous integrated circuit (IC) tester includes a set of channels interconnected by a runtime bus. Each channel accesses a separate terminal of an IC device under test (DUT) for carrying out test activities during successive cycles of a test. During each cycle of a test, each channel may transmit a test signal to the DUT, sample a DUT output signal and store sample data representing the logic state of the DUT output signal, and/or compare previously stored sample data to expected patterns to determine if the DUT is operating correctly. Any channel may be programmed to place a MATCH code on the runtime bus when it recognizes, or fails to recognize, a particular logic pattern in the DUT output signal. Other channels may be programmed to pause their comparison activities until they receive the MATCH code over the runtime bus. Thus a DUT output signal event detected by any one channel triggers test activities by other channels.

Abstract: A self-calibrating programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A conversion table converts input data indicting a desired phase shift between the reference signal and the output signal into output data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The phase shifter includes calibration circuitry that convert the phase shifter into an oscillator by feeding the output signal back as input to the tapped delay line and adjusting relationships between the conversion table input and output data so that the period of the output signal has a desired linear relationship to the input data value.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands.

Abstract: An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node and a time relative to the start of the test that each action is to be taken. The actions may include transmitting a test signal to the IC or sampling an output signal produced by the IC. Before starting the test, the tester converts the description into a set of algorithms for generating test vectors and stores each algorithm in a separate processing node. The test is organized into a succession of test cycles and during the test, each node executes its stored algorithm, generating a separate test vector at the beginning of each test cycle. The test vector indicates an action to be taken by that node during the following test cycle along with a time during the test cycle that the action is to be taken.

Abstract: A timing signal generator includes a voltage controlled oscillator (VCO), a logic circuit, N set circuits and N reset circuits and a bistable latch circuit. The VCO produces a set of N reference signals frequency locked to a reference clock signal and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit asserts ones of N set signals and N reset signals selected by input control words. Each set circuit receives one of the N set signals and one of the N reference signals and briefly couples an output node to high logic level source in response to a leading edge of the received reference signal when its received set signal is asserted. Each reset circuit receives one of the N reset signals and one of the N reference signals and briefly couples the output node to low logic level source in response to a leading edge of its received reference signal when it reset signal is asserted.

Abstract: A timing signal generator produces a timing signal having one or more pulses of adjustable phase relative to pulses of a stable reference clock. The timing signal generator employs a low jitter retriggerable oscillator to produce a set of tap signals. The tap signals are frequency locked to the reference clock signal but are evenly distributed in phase. The timing signal generator times the pulses of its output timing signal using pulses of the various tap signals as timing references. Each cycle of the oscillator is triggered by a pulse of the reference clock signal to minimize timing signal jitter. Phase lock loops frequency lock the tap signals to the reference clock and ensure predictability of the timing signal pulse timing relative to the reference clock signal.

Abstract: An embodiment of the present invention is a retriggered oscillator timebase including a phase lock loop controlled ring for direct retriggering by a reference oscillator. The ring has taps at various successive stages that are output to an on-the-fly selector that can add any ten-bit value to a current-tap selection to enable a next-tap selection. Such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency. Ring outputs are also used to drive two other retriggered rings for a plurality of NANO timing generators. The use of two rings allows retriggering of one of the rings before the other has completed a whole one-shot cycle. An on-the-fly selector subtracts a value from a present "NANO" select to a next "NANO" select to convert back the timebase to the fixed reference frequency for phase and frequency comparison. The subtraction acts as a frequency multiplication whose output "t.sub.0fx " is equal to the reference frequency.

Abstract: A device and method are presented which allows the precise generation of signals within an integrated circuit that are calibrated to an external reference signal. The device consists of a ring oscillator which generates a calibration signal oscillating at a first frequency and a power source that supplies a compensated power signal to the ring oscillator. The first frequency is variable based on the voltage of the compensated power signal. A phase detector is used to detect the relative phase of the calibration signal and the external reference signal. The compensated power signal is also used for critical data paths within the integrated circuit where precise timing is required. In a tester, a plurality of signals may be extracted from the ring oscillator using a series of taps. These signals will oscillate at the same frequency as the calibration signal, but will be phase shifted. The signals may be combined with multiplexors to form a test signal which is applied to a device under test (DUT).