Abstract: A system-on-a-chip with a variable bandwidth bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur.

Abstract: A system-on-a-chip with a variable clock rate bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively adjusts the clock rate of the bus based on the timing value.

Abstract: A computing system employs an unicode driver to access and control peripheral devices by abstracting commands and status data to a level above register sets of similar but potentially incompatible peripheral devices. A unicode may be generated by an operating system or the unicode driver. Unicodes are routed by a device configuration interface that passes the unicodes between the unicode driver and peripheral devices. The peripheral devices include command decoders for performing conversion between unicodes and device-specific instructions. The use of unicode drivers eliminates duplicate driver code and simplifies device configuration for the computing system.

Abstract: A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as latches, or registers. The miscellaneous logic is coupled to multiple stages of scan cells. The multiple stages can be used as a buffer while the last stage of scan cells are scanned out. A predetermined stage of scan cells are coupled together to form a scan path where data from the miscellaneous logic can be outputted to an external memory. In one embodiment, the predetermined stage is the last stage of scan cells. A trigger signal is used to shift the data from the miscellaneous logic to the next stage of scan cells. Once the last stage of scan cells are loaded, a clocking signal can be provided so that the data in the predetermined stage of scan cells is scanned out. The present invention provides among other things, a graceful way to capture data from miscellaneous logic of the microcontroller using scan hardware.

Abstract: The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an “initial state” of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an “initial state” of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer.

Abstract: A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.

Abstract: An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.

Abstract: A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device.

Abstract: A computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically configurable to form two or more separate communication paths. The plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other. The plurality of communication ports may also be dynamically configurable to form two or more communication rings.

Abstract: A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic.

Abstract: A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution.

Abstract: An on-chip thermometer and methods for using the on-chip thermometer to measure a local temperature and to operate an integrated circuit. The on-chip thermometer comprises a clock circuit, a temperature responsive circuit, and a counter. The clock circuit operates at a fixed frequency and generates a fixed frequency clock signal. The temperature responsive circuit, when enabled, generates a signal dependent on local temperature. In response to receiving the clock signal, the temperature responsive circuit generates an output signal. The counter is coupled to receive the output signal from the temperature responsive circuit and the clock signal. The counter then generates a value indicative of a local temperature of the integrated circuit.