Abstract: Provided herein are mutants of estrogen receptor alpha ligand binding domain (ER-LBD), and chimeric proteins including such mutant ER-LBD. Also provided are methods of modulating transcription and modulating localization of such chimeric proteins.

Abstract: Provided herein are mutants of estrogen receptor alpha ligand binding domain (ER-LBD), and chimeric proteins including such mutant ER-LBD. Also provided are methods of modulating transcription and modulating localization of such chimeric proteins.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency, such as accuracy of learning, accuracy of prediction, speed of learning, performance of learning, and energy efficiency of learning. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Each compute element has processing resources and memory resources. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Stochastic gradient descent, mini-batch gradient descent, and continuous propagation gradient descent are techniques usable to train weights of a neural network modeled by the processing elements. Reverse checkpoint is usable to reduce memory usage during the training.

Abstract: Described herein are chimeric proteins, specifically membrane-cleavable chimeric systems. Also described herein are nucleic acids, cells, and methods directed to the same.

Abstract: A reel carrier that includes a pallet having a platform bound by a frame and a shaft. The carrier includes a reel that is supported on the shaft. The reel includes a round drum rotatable about the shaft, wherein the rotation may be in a forward and/or a reverse or backward rotational direction. The carrier also includes a motor operably coupled to cause rotation of the drum and may be further operably coupled to cause deployment and/or retraction of one or more wheels included with the pallet, wherein the motor also controls locomotion of the one or more wheels.

Abstract: The present invention relates generally to the field of pump cleaning and unclogging. More specifically, the present invention relates to a tool which allows a user to unclog and remove rags, cloth materials, debris, or other obstructions from submersible and master-station pumps. Further, the invention can be used either as a hand tool or as an attachment to a crane or other machine for power assisted pulling, unclogging, and removal of rags, cloth materials, debris, and other obstructions.

Abstract: The present invention relates generally to the field of pump cleaning and unclogging. More specifically, the present invention relates to a tool which allows a user to unclog and remove rags, cloth materials, debris, or other obstructions from submersible and master-station pumps. Further, the invention can be used either as a hand tool or as an attachment to a crane or other machine for power assisted pulling, unclogging, and removal of rags, cloth materials, debris, and other obstructions.

Abstract: A reel carrier that includes a pallet having a platform bound by a frame and a shaft. The carrier includes a reel that is supported on the shaft. The reel includes a round drum rotatable about the shaft, wherein the rotation may be in a forward and/or a reverse or backward rotational direction. The carrier also includes a motor operably coupled to cause rotation of the drum and may be further operably coupled to cause deployment and/or retraction of one or more wheels included with the pallet, wherein the motor also controls locomotion of the one or more wheels.

Abstract: Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

Abstract: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Abstract: The product of the present invention comprises flexible tray cables and metal-clad cables designed for use with adjustable speed drives, and terminations coupled therewith. The cables comprise, generally, three phase conductors, three ground conductors and fillers, and are wrapped with copper tape and other elements. The terminations comprise a plurality of connectors and a plurality of flexible, tinned-copper braids acting as the shield termination for the copper tape. More detailed and other embodiments of the present invention are disclosed in the specification hereof.

Abstract: Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

Abstract: Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

Abstract: A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

Abstract: Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top surface of substrate (1102) uses between about 30% to 90% of its area for connecting lines (1104), and only the remainder for members/rings (1105) and terminals (1106). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals (1106) serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings (1105) are the conductive pins (1107), which serve as anchors for the solder bodies/balls (1108). Pins (1107) are substantially insensitive to the thermomechanical stresses, which occur in device (1100) during assembly, testing and operation.

Abstract: A radial arm saw glass cutting attachment including an arm having an orthogonal and a radially oriented glass cutter. The arm attaches to the radial arm saw blade attachment shaft and the shaft is oriented orthogonally to a glass plate being prepared for cutting for the purpose of producing circular or annular cut patterns, or the shaft is oriented parallel to the plane of the glass plate for the purpose of producing linear and angularly disposed linear cuts. A graduated scale which enables setting radius or diameter of a cut circle, and a thumbscrew lock for the freely sliding orthogonal cutter are included.

Abstract: A system for analogue to digital conversion comprising a means (4) for receiving an input analogue signal, a dither generator for adding a dither signal and an analogue to digital converter (2) for converting the combined input signal and dither signal to a digital value, characterized in that the dither generator provides a dither signal of a form comprising a first periodic dither signal having superimposed and being shaped by a second signal having at least one component which varies the first periodic dither signal over at least one quantization interval of the analogue to digital converter.