Abstract: A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e.

Abstract: In a current pump, three separate current sources, each providing an identical current, are used. A first current pump is provided between an output load and a positive power supply terminal to provide a positive current to a load. To enable the current pump to provide a zero current to the load or withdraw a current from the load, second and third current pumps are provided in parallel between the load and a ground terminal. Associated switches couple these second and third current sources to the load. Thus, three states of the current pump are available which provide either a positive current, a negative current, or a zero current to a load.

Abstract: The present invention includes circuitry implemented in gallium arsenide technology for generating various substantially constant reference voltage and a substantially constant reference current for applications thereof as needed.

Abstract: A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay.

Abstract: An output buffer provides high current at an output for only a brief period, while after this brief period the output buffer only supplies a limited amount of current to the subsequent stage. One embodiment of this inventive output buffer utilizes the inherent delay of an inverter and a high current FET device, arranged to form a feedback circuit, to switch off high current supplied to the subsequent stage afer a brief period. This brief period allows the output of the output buffer to supply the necessary current and voltage to switch the subsequent stage. A low current FET device in the output buffer then provides the necessary low current to maintain the state of the subsequent stage without supplying current unnecessary for the proper operation of the subsequent stage.

Abstract: A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.

Abstract: A multiplexing type circuit includes circuit portions having input and output leads associated therewith, to allow testing of the individual circuit portions, and further includes laser programmable fuses which allow selective disconnection of certain input and output leads as chosen to disconnect circuit portions from the overall circuit as appropriate.

Abstract: An improved logic circuit is disclosed, of the type in which one or more input signals, generated by one or more input signal generator circuits, are referenced to a threshold voltage, determined by a threshold voltage generator circuit, to determine whether said one or more input signals are in a high or low state. In this improved logic circuit, the time constants of the input signal generator circuits are matched with those of the threshold voltage generator circuit so that any power supply perturbations commonly applied to the input signal generator circuits and threshold voltage generator circuit, such as due to the switching on or off of output loads, will result in these circuits having substantially identical frequency responses and amplitude versus time responses.

Abstract: The present invention includes circuitry wherein a pair of voltage supply terminals are included, with a first current source connected to one voltage supply terminal and a second current source connected to the other voltage supply terminal. A load connects the first and second currect sources. A field effect transistor has a first current handling terminal connected between the first current source and load, a second current handling terminal connected to the other voltage supply terminal, and a current control terminal connected between the load and the second current source. The second current source is of the type wherein the current thereacross is substantially independent of changes in voltage thereacross.

Abstract: The present electrical circuit is capable of coupling operation between other circuits which may have different signal levels, such as small-swing ECL-like signals and large-swing TTL-like signals.

Abstract: A semiconductor device includes as part of the integrated circuit thereof a test structure which allows testing of the semiconductor device through the device pins, to allow adjustment of various parameters of the circuit if desired for obtainment of optimum performance, and with the circuit being operable under normal conditions without degradation in relation to its optimum design situation.