Abstract: Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).