Abstract: A methodology to increase buffer capacity of an Ethernet switch uses an intelligent packet buffer at external ports of the Ethernet switch. Each intelligent packet buffer may include buffer logic and a buffered Ethernet port coupled to an internal Ethernet port of a switching element. The intelligent packet buffer may use a memory controller to access a random access memory using page mode access, and may write portions of a packet stream to a logical buffer in the random access memory that is dedicated to the internal Ethernet port. The intelligent packet buffer may forward the packet stream from the logical buffer to the internal Ethernet port. The logical buffer may represent a virtual output queue of the Ethernet switch associated with the internal Ethernet port. The intelligent packet buffer may be dimensioned with corresponding buffer logic and random access memory capacity to buffer one or more external ports.

Abstract: A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.

Abstract: A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.

Abstract: A system for connecting optical modules in an optical network may comprise a printed circuit board, two cages, and two connectors. The printed circuit board may house electronic circuitry and a plurality of electronic components. The printed circuit board may have a component side and a solder side. The two cages may be mounted back-to-back on opposite sides of the printed circuit board, each cage having a connector end and an I/O end. The two connectors may be mounted back-to-back on opposite sides of the printed circuit board. Each of the two cages may be configured to guide an optical module into the respective connector. Each of the two cages may be mounted at an angle from the respective surface of the printed circuit board such that the respective I/O ends of the two cages are farther apart than the respective connector ends of the two cages.