Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other intergrated curcuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. A capacitor element is used to provide programming voltages to the non-volatile memory cell. And in one embodiment, the non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node, such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses with the change in resistivity representing a change in logic state, and such that the capacitor element is configured to provide the voltage pulses to the programming node.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A non-volatile memory cell and associated programming methods are disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. A capacitor element is used to provide programming voltages to the non-volatile memory cell. And in one embodiment, the non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node, such that the antifuse element is configured to have reduced resistivity after the programming node is subjected to one or more voltage pulses with the change in resistivity representing a change in logic state, and such that the capacitor element is configured to provide the voltage pulses to the programming node.

Abstract: A method and related embedded memories are disclosed for utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element. To guide the breakdown locations within the dielectric, one or more voltage gradients are generated within the antifuse element to concentration current flow.

Abstract: A method and related embedded memories are disclosed for utilizing a plurality of voltage pulses to program non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. To write the antifuse element, a plurality of voltage pulses are used to provide a rapid series of charge flows through the antifuse element. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element.