Abstract: A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

Abstract: A method and apparatus are provided for scheduling the transmission of cells and frames in a communications network. The transmission of cells and frames are scheduled utilizing a selected scheduling algorithm. The cell/frame scheduling algorithm includes the step of identifying a frame or cell transmission type. Responsive to the identified frame or cell transmission type, a frame multiplier value is identified. A target transmission time is calculated for the frame or cell transmission type utilizing the identified frame multiplier value. A method and apparatus optionally are provided for scheduling the transmission of packet pairs.

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit.

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit.

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit.

Abstract: A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.

Abstract: A method and apparatus are provided for detecting and controlling data stream splicing in a stream of multimedia digital data over a distribution communications network. Sequential transport stream packets are obtained. Predetermined fields of each transport stream packet are interrogated to identify a splice in the data stream. A predetermined task is initiated responsive to an identified splice. In accordance with feature of the invention, one predetermined task initiated responsive to the identified splice includes masking the interrogated predetermined fields to mask the splice in the data stream.

Abstract: A method and apparatus are provided for scheduling the transmission of cells of a plurality of data streams in a communications network. An earliest deadline first (EDF) scheduler is provided for scheduling the transmission of cells of a plurality of data streams in a communications network to ensure that the connection or data stream with the earliest deadline is transmitted first. Each of the multiple data streams has a delay bound or deadline. Data of each data stream is enqueued to a corresponding data cell queue. A timing wheel time slot based on an identified target transmission time for each data cell queue is calculated utilizing an addition of a maximum delay value. A move forward timing mechanism includes a scan forward feature to identify a succession of virtual connection or data stream cell queues for transmission. A multiple tier cell scheduler is provided that includes at least two scheduling timing wheels.

Abstract: A method and apparatus are provided for resource allocation with guarantees. A resource allocator is coupled to a controller. The resource allocator allocates resources between a plurality of arrival processes. A dedicated resource pool and a shared resource pool are provided. When an arrival process is identified, the resource allocator obtains a predefined characterizing value for the identified arrival process. Responsive to the obtained predefined characterizing value, resource from one of the dedicated resource pool or the shared resource pool is allocated to the arrival process. The controller is utilized for tracking resource use and for providing the predefined characterizing value for each of the plurality of arrival processes. The dedicated resource pool has a predetermined capacity greater than or equal to the total of all the low threshold values for each of the arrival processes.

Abstract: A method and apparatus are provided for enhanced scatter mode allowing user data to be page aligned in a memory. An adapter is coupled between a data communications network and the memory. A data packet including protocol header bytes is received from a data communications network by the adapter. A variable amount of data is specified for a first scatter page that contains the protocol header bytes. Subsequent sequential pages from the received data packet are transferred, for example, by direct memory access (DMA) operations, to real page addresses in the memory with the sequential pages transferred being page aligned in the memory. A page address is written to a DMA list stored in an adapter memory for the sequential pages transferred. A count value is incremented in a packet header of a number of pages transferred for each sequential page transferred.

Abstract: An improved method and apparatus are provided for queuing and triggering the flow of data across ATM networks. A connection is established between an insertion server and a client multiplexer. The insertion server prepares a timing response and establishes a transmit queue threshold for a pending trigger point for inserting data. The insertion server enqueues data. Responsive to receiving a timing request from the client multiplexer, the insertion server sends the timing response. Responsive to receiving a stream request from the client multiplexer, the insertion server transfers the enqueued data. The client multiplexer includes a timer for identifying an offset time between sending the timing request and receiving a timing response from the insertion server. The client multiplexer uses the offset time to set a count down timer for sending the stream request. The client multiplexer processes the data transferred by the insertion server and optionally sends a stop stream command to the insertion server.

Abstract: A method and apparatus are provided for scheduling the transmission of cells of a plurality of data streams in a communications network. A best effort scheduler is provided for scheduling the transmission of cells of a plurality of data streams in a communications network. The best effort scheduler includes a best effort operational mode and can include more than one timing wheel. When the best effort scheduler includes more than one timing wheel, then the priority of the best effort timing wheel is lower than the priority of the other timing wheel or wheels. Data of each data stream is enqueued to a corresponding data cell queue. A target next transmission time for each data cell queue is calculated utilizing predetermined logical channel descriptor parameters. A lower priority or a higher priority timing wheel is selected and a timing wheel time slot is calculated based on an identified target transmission time for each active data cell queue.

Abstract: An improved method and apparatus are provided for producing transmission control protocol (TCP) checksums using internet protocol (IP) fragmentation. A transmission control protocol module receives packet data to be transmitted and prepares a first internet protocol data fragment without a checksum for the received packet data. The first internet protocol data fragment is transmitted. Collecting checksum is performed during the transmission of the first internet protocol data fragment. Then an internet protocol header fragment including the collected checksum is transmitted.

Abstract: A mixed-endian computer system enhanced to manage I/O DMA without a software DMA performance penalty. A mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian system, as enhanced, performs one of two well-defined DMA operations based on control bits either in the DMA control register or in a bit vector associated with each page of processor storage. This invention also describes means for treating I/O registers as if they were of the endian of the executing processor, instead of the more typical need to have the register operate in a particular endian.

Abstract: A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.

Abstract: A method and apparatus are provided for generation of predicted responses in a computer communications network system. A server in the computer communications network system predicts the client's next request based on the present client's request. The server sets a trigger that recognizes a match of the client's predicted request. When a client's predicted request arrives, the trigger sends the response. Additionally, the server associates a timeout action with the predicted response so that if a predicted request is not received within the timeout interval or other events occur before the predicted request arrives, the triggered response is removed and an alternative action is performed.

Abstract: A method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system are disclosed. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.

Abstract: A configurable variable cache includes a cache memory for storing data. The cache memory is selectively configured into a variable number of variable size lines. At least one user is connected to the cache memory. An addressing function coupled to the cache memory is used for accessing the lines of the cache.

Abstract: A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

Abstract: Method and apparatus are provided for segmenting a multiple program multimedia digital data stream for transmission over a distribution communications network. Each program multimedia digital data stream includes sequential transport system (TS) packets with program clock references (PCRs) at a set time interval and a program identification (PID) associated with the PCRs. The multiple program multimedia digital data stream is received. The TS packets are decoded to identify the program clock references (PCRs). A selected number N of TS packets are identified. The multimedia digital data stream into frames responsive to both the identified number N of TS packets and the identified PCRs. A program identification (PID) associated with one of the PCRs is selected for timing the transmission of segmented multiple program multimedia digital data stream.