Patents by Inventor Gary Stephen Ditlow

Gary Stephen Ditlow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable logic array and method for its design using a three step approach
    Patent number: 5872462
    Abstract: A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or more sections. A modified gap cell recombines the product terms before propagating the signal into an array.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output
    Patent number: 5811988
    Abstract: An apparatus for redirecting late-entering PLA input signals to avoid holding up the entire PLA while the late-entering signals are processed, and a method for designing the same.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: September 22, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • Reduced power PLA
    Patent number: 5719505
    Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: February 17, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output
    Patent number: 5717344
    Abstract: An apparatus for redirecting late-entering PLA input signals to avoid holding up the entire PLA while the late-entering signals are processed, and a method for designing the same.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: February 10, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke
  • Method of power reduction in pla's
    Patent number: 5712790
    Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: January 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Gary Stephen Ditlow, Paul David Kartschoke