Abstract: An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

Abstract: An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.

Abstract: A circuit realizable on a single substrate, for interfacing between a digital processor and a raster scanned, video display particularly suitable for games, or the like. In the presently preferred embodiment, up to thirty-two objects may be simultaneously displayed. Content addressable memories (CAMs) which compare beam location with desired object location are employed to locate objects on the display. Fewer than thirty-two CAMs are employed to locate thirty-two objects with the circuit's "grouped major system". The display circuit includes another subsystem ("minor system") for displaying patterns with a minimum of control by the processor.

Abstract: A programmable CMOS integrated circuit counter which compensates for fast or slow quartz crystal oscillators, particularly suited for watches. The circuit includes fuses which are programmed for a particular crystal; the programming is a function of the frequency deviation of the crystal oscillator from the standard frequency for that crystal oscillator. In the described watch circuit which employs a nominal 32,768hz crystal, compensation within .+-. 1ppm is obtained.