Abstract: A linear optocoupler (71) having a light emitting diode (28) and a detector diode (29) formed on a common semiconductor substrate (33). Light emitted by the light emitting diode (28) is transmissive to semiconductor substrate (33). A layer of light reflective material (34) is formed on a side opposite from which the light emitting diode (28) and the detector diode (29) on the semiconductor substrate (33). A portion of light emitted by the light emitting diode (28) transmits through the semiconductor substrate (33) to be reflected by the layer of light reflective material (34). The reflected light transmits through the semiconductor substrate (33) to be received by the detector diode (29). A photo detector diode (61) and the semiconductor substrate (33) including the light emitting diode (28) and the detector diode (29) are mounted on a lead frame (51) co-planar to one another. A light flux coupling media (76) couples light from the light emitting diode (28) to the photo detector diode (29).

Abstract: A method for building a compilable static RAM (SRAM). A central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a databus interface. A memory block macro (35) is built which includes a block of memory, precharge circuits, multiplexers, read/write multiplexers, and sense amplifiers. If multiple memory blocks are used a block deselect circuit (39) and row/block decoders (38) must be added to the memory block macro (35). A row and block deselection process is used in the SRAM architecture to simplify compilability and enhance speed.

Abstract: A static random access memory (SRAM) that is configurable for different word widths and memory sizes, and a method for forming the physical layout with blocks of a SRAM are described. In the physical layout of the SRAM, a central block structure (54) is formed which includes clock buffers (28), a delayed clock buffer (29), row address buffers (27), row deselect circuits (21), row driver circuits (22), output level translators, and a data bus interface. Memory block macros (35) are formed that include a block of memory, precharge circuits, read/write multiplexers, and sense amplifiers. Memory block macros (35) are symmetrically located around the central block structure (54), and may also include a block deselect circuit (39) and rox/block decoders (38) if multiple memory blocks are used. A deselection process may be used in which the SRAM selects a bit or word by deselection.

Abstract: A power efficient transistor (11) which operates in or near saturation having a base (16), a collector (17), and an emitter (18). A first transistor (12) having a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). The first transistor (12) is biased to operate in or near saturation under quiescent conditions. A plurality of transistors (13) are incrementally enabled or disabled to maintain the transistor (11) in or near saturation under all operating conditions. Each of the transistors (13) have a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). A plurality of drive transistors (14), enable or disable a corresponding one of each transistor of the transistors (13). Each drive transistor of the drive transistors (14) is enabled at a different voltage thereby incrementally enabling and disabling each transistor of transistors (13) maintaining transistor 11 in or near saturation.

Abstract: A circuit and method for reducing a gate voltage of a transmission gate to prevent overvoltage that could damage or affect reliability of the transmission gate. The transmission gate resides in a charge pump circuit (41) coupled to a capacitor for generating a voltage greater than a power supply voltage. A buffer (44,45) receives a control signal and couples to a gate terminal of the transmission gate. The buffer (44,45) includes a power supply terminal that is coupled to a variable voltage reference (43). The variable voltage reference (43) provides a voltage that reduces the gate voltage of the transmission gate when an output voltage of the charge pump circuit reaches a predetermined voltage. The variable voltage reference (43) reduces a voltage range between logic levels provided by the buffer (44,45) to protect the transmission gate from an excessive voltage.

Abstract: A memory cell sense technique for sensing a logic state of a memory cell. An output level translator (33) which can be preset to a predetermined logic state is utilized. A current source circuit (24) and a current sink circuit (26) change memory cell sensing into two distinct modes. In the first mode, the memory cell logic state is identical to the preset output logic state. The memory cell generates a differential voltage which is countered by a differential voltage created by the current source and current sink circuit. Inputs to a sensing circuit common mode and non-complemented output (44) remains in the preset logic state. In the second mode, the current source circuit and current sink circuit aid the memory cell in generating a differential voltage. The sensing circuit senses the differential voltage and changes the non-complemented output (44) from the preset logic state.

Abstract: A deselect circuit (10) receiving a variable number of input signals which enables an output stage to generate a logic state signifying a deselect condition at a deselect output (12). The deselect circuit (10) operates synchronously having a clock signal (21) and inverted clock signal (22) to control internal timings. The deselect output (12) is preset to a logic state signifying a select condition prior to starting a deselect sequence, thus eliminating the need for circuitry to generate the select condition. The path for generating a deselect condition comprises a transmission gate which couples the inverted clock signal to a driver stage, a multiple input switch which couples the driver stage to a output stage, and the output stage which generates a logic state signifying a deselect condition at the deselect output (12). A sensing circuit is used to sense the select condition and enable a second driver stage to maintain the select condition.

Abstract: A self-test that is variable to test an SRAM that is embedded on a semiconductor die is achieved. The self-test is performed by a modular self-test circuitry that can be varied to permit generating addresses, and data patterns for various SRAM architectures and sizes. An address block develops addresses which define a test location or test word within the SRAM. The address block also develops a time delay which is used during a data retention test. A data block develops test patterns that are written into SRAM test locations. The data block also analyzes data read from SRAM test locations or test words. Both the address block and the data block are formed by combining a number of individual address or data cells, thereby providing addresses and data patterns for a variety of different SRAM configurations. A control block operates the address block, the data block, and the SRAM to perform two memory tests.

Abstract: A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delayed clock signal (15) for enabling first buffer circuit (12), a gated transmission means (13) for decoupling first buffer circuit from second buffer circuit (14), second buffer circuit (14) for driving capacitive loads, and a means for delaying driver output (16) for enabling gated transmission means (13). The decode circuit (10) is built for simplifying synthesis of the layout of a configurable decode circuit for varying configurations. The configurable decode optimizes performance by reducing the number of circuits in the critical delay path and minimizing capacitive loading on internal circuit nodes.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.