Abstract: A system for testing digital circuit units at the design speed of the circuit. A first memory stores a minimized set of optimum generated predetermined test patterns for application to a unit under test. A second memory stores expected signature patterns corresponding to signature patterns that are derived from the unit under test in response to the predetermined test patterns when the unit under test is functioning properly. A signature analyzer derives signature patterns from a unit under test in response to the application of the test patterns to the unit. A comparator compares the derived signature patterns with the expected signature patterns and provides an indication of the results of the comparison.