Abstract: Link speed recovery in a data storage system in accordance with the present description includes, in one aspect of the present description, repeating performance of a main loop of sequential link speed recovery commands a predetermined maximum number of times. In one embodiment, main loop performance of link speed recovery commands includes repeating performance of a subloop of sequential link speed recovery commands within each main loop performance a predetermined maximum number of times. As a result of repeating performance of a subloop of sequential link speed recovery commands within each main loop performance, and repeating performance of a main loop of sequential link speed recovery commands in accordance with one embodiment, reliability of link speed recovery to full link speed may be improved. Other aspects and advantages may be realized, depending upon the particular application.

Abstract: A system for generating bus signals for a plurality of remote stations. Bus data packets are comprised of a plurality of data blocks. Each data block is directed to a remote station. The position of each data block in the data packet identifies the remote station to which the data block is directed. Each of the remote stations receives each data packet substantially synchronously. The remote stations decode the data packets to determine the type of data packet and identify the content of the data packet directed to it. Each remote station loads the corresponding content from the data packet. Each of the remote stations can then generate output signals based on the data packet content substantially synchronously with the other remote stations.

Abstract: A system for generating bus signals for a plurality of remote stations. Bus data packets are comprised of a plurality of data blocks. Each data block is directed to a remote station. The position of each data block in the data packet identifies the remote station to which the data block is directed. Each of the remote stations receives each data packet substantially synchronously. The remote stations decode the data packets to determine the type of data packet and identify the content of the data packet directed to it. Each remote station loads the corresponding content from the data packet. Each of the remote stations can then generate output signals based on the data packet content substantially synchronously with the other remote stations.

Abstract: An apparatus, system, and method are disclosed for dual master LED (Light Emitting Diode) control. Two hosts are connected to and redundantly control the operation of an LED. Communication modules coupled to the two hosts facilitate communication between the two hosts without affecting the normal operation of the LED. This is done by sending pulses between the two hosts such that the hosts can be synchronized as well as communicate information to one another across the LED channel. The pulses have a small width such that any affect on the LED is imperceptible to humans.

Abstract: An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source.

Abstract: A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

Abstract: A system and method track and control the prefetching of blocks of a data stream in a PCI bus system, avoiding unnecessary prefetches. The data stream is grouped into major blocks which comprise a fixed plurality of contiguous blocks. A prefetch buffer stores the blocks of data prefetched from a PCI data source for transfer to a requester. First and second associated prefetch count storage locations store first and second counts initialized by prefetch initialization logic. The first count represents the number of blocks of data of a major block of the data, and the second count represents the total number of the blocks of the data stream to be prefetched, less the initialized number of blocks of the first count. As each block of data is prefetched, a prefetch counter decrements the first count by a number representing the block of data.

Abstract: Disclosed is a bridge system and method for prefetching data to return to a read request from an agent. The bridge system includes at least one memory device including a counter indicating a number of prefetch operations to perform to prefetch all the requested data, a first buffer capable of storing prefetch requests, and a second buffer capable of storing read data. Control logic implemented in the bridge system includes means for queuing at least one prefetch operation in the first buffer while the counter is greater than zero. The control logic then executes a queued prefetch operation, subsequently receives the prefetched data, and stores the prefetched data in the second buffer. The stored prefetched data is returned to the requesting agent.

Abstract: A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a channel adapter at one PCI bus that issues read commands, a data source coupled to a second PCI bus, and a prefetch buffer that prefetches the blocks of read data. A prefetch counter posts the remaining number blocks to be read and transferred, posting the prefetch count at a storage location of a storage memory mapped to a prefetch location in the prefetch buffer. The prefetch count is written to the storage location by a prefetch count write command. The system for flushing stale data from the prefetch buffer comprises a key detector for sensing an unique identifier of the prefetch count write command.

Abstract: Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Abstract: Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent.

Abstract: Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.

Abstract: Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.