Patents by Inventor Gaspar Mora Porta

Gaspar Mora Porta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949595
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta
  • Publication number: 20240028400
    Abstract: In various examples, a transaction type of a transaction from a processing resource of a plurality of processing resources sharing a bus may be determined and used to track bandwidth usage for the processing resource with respect to a time slot. Transactions that indicate usage of downstream bandwidth may be distinguished from transactions that do not indicate usage of downstream bandwidth. Bandwidth usage for a time slot may be tracked using one or more counters. The system may block or permit transactions from reaching the bus based at least on the counter exceeding a threshold value. The total allocation of bandwidth to the processing resources sharing a bus may be limited to a value that is less than a maximum capability of the bus to allow for headroom. Bandwidth coming from different lines and/or lanes and belonging to the same processing resource may be shared.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Gaspar Mora Porta, Blaise Fanning, Michael Allen Parker, Manikandan Chandrasekaran, Adarsha Rao S J, Raghuram L
  • Patent number: 11722438
    Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: John Greth, Arvind Srinivasan, Robert Southworth, David Arditti Ilitzky, Bongjin Jung, Gaspar Mora Porta
  • Patent number: 11366588
    Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Nicolae O. Popovici, Charles A. Giefer, Gaspar Mora Porta, Thomas Willhalm
  • Patent number: 11055247
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Gaspar Mora Porta, Michael A Parker, Roberto Penaranda Cebrian, Albert S Cheng, Francesc Guim Bernat
  • Publication number: 20210058334
    Abstract: Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: John GRETH, Arvind SRINIVASAN, David ARDITTI ILITZKY, Robert SOUTHWORTH, Gaspar MORA PORTA, Scott DIESING, Bongjin JUNG, Prasad SHABADI
  • Publication number: 20210058343
    Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: John GRETH, Arvind SRINIVASAN, Robert SOUTHWORTH, David ARDITTI ILITZKY, Bongjin JUNG, Gaspar MORA PORTA
  • Publication number: 20200336424
    Abstract: An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Yonatan Meir Levitt, Gaspar Mora Porta
  • Publication number: 20200050569
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 13, 2020
    Inventors: Gaspar MORA PORTA, Michael A PARKER, Roberto PENARANDA CEBRIAN, Albert S. CHENG, Francesc GUIM BERNAT
  • Patent number: 10547527
    Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Raj K. Ramanujan, Gaspar Mora Porta, Daniel Rivas Barragan
  • Publication number: 20190004701
    Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.
    Type: Application
    Filed: July 3, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Nicolae O. Popovici, Charles A. Giefer, Gaspar Mora Porta, Thomas Willhalm
  • Publication number: 20180241802
    Abstract: Technologies for network switch based load balancing include a network switch. The network switch is to receive messages, route messages to destination computing devices, receive a request to perform a workload, and receive telemetry data from a plurality of server nodes in communication with the network switch. The telemetry data is indicative of a present load on one or more resources of each server node. The network switch is further to determine channel utilization data for each of the server nodes, select, as a function of the telemetry data and the channel utilization data, one or more of the server nodes to execute the workload, and assign the workload to the selected one or more server nodes. Other embodiments are also described and claimed.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Gaspar Mora Porta, Daniel Rivas Barragan
  • Publication number: 20180097743
    Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Raj K. Ramanujan, Gaspar Mora Porta, Daniel Rivas Barragan
  • Patent number: 9294403
    Abstract: Methods and apparatus relating to techniques for controlling resource utilization with adaptive routing are described. In one embodiment, an output port for transmission of an incoming message that is to be received at an input port is determined at routing logic. The routing logic selects the output port from a first output port and a second output port based on congestion information that is detected at one or more other routing logic communicatively coupled to the routing logic. The first output port provides a deterministic route for the incoming message and the second output port provides an adaptive route for the incoming message. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Andres Mejia, Donglai Dai, Gaspar Mora Porta
  • Publication number: 20150003247
    Abstract: Methods and apparatus relating to techniques for controlling resource utilization with adaptive routing are described. In one embodiment, an output port for transmission of an incoming message that is to be received at an input port is determined at routing logic. The routing logic selects the output port from a first output port and a second output port based on congestion information that is detected at one or more other routing logic communicatively coupled to the routing logic. The first output port provides a deterministic route for the incoming message and the second output port provides an adaptive route for the incoming message. Other embodiments are also disclosed.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Andres Mejia, Donglai Dai, Gaspar Mora Porta
  • Patent number: 8867559
    Abstract: An apparatus that includes input ports, input buffers coupled with respective input ports, output ports, and routing control circuitry coupled with the input ports, the input buffers and/or the output ports. The plurality of input buffers and the plurality of output ports, the routing control circuitry to maintain a two-tier priority scheme having at least two queues for prioritizing requests stored in the plurality of input buffers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Donglai Dai, Andres Mejia, Gaspar Mora Porta
  • Publication number: 20140086260
    Abstract: An apparatus that includes input ports, input buffers coupled with respective input ports, output ports, and routing control circuitry coupled with the input ports, the input buffers and/or the output ports. The plurality of input buffers and the plurality of output ports, the routing control circuitry to maintain a two-tier priority scheme having at least two queues for prioritizing requests stored in the plurality of input buffers.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: DONGLAI DAI, Andreas Mejia, Gaspar Mora Porta