Abstract: A method for selecting a target cell by a user equipment (UE), includes: detecting a movement of the UE based on a change in a location of the UE and a change in a measured signal power of a serving cell; determining personalized data of a user based on a plurality of user contextual parameters; predicting a destination of the user, and one or more target cells across a path of the user to the destination based on the determined personalized data of the user and the detected movement of the UE; and selecting the target cell from the one or more target cells, based on an artificial intelligence (AI) model. The AI model is configured to update weights of one or more network quality parameters.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: The present disclosure relates to a heating, ventilating, and air conditioning (HVAC) unit configured to supply conditioned air to a conditioned space. The HVAC unit includes a first exhaust fan capable of operating at variable speeds and a second constant-speed fan. The HVAC unit also includes a controller configured to determine a target airflow to be provided to the conditioned space, cause actuation of the first exhaust fan at a variable fan speed when the target airflow is greater than zero, and cause actuation of the second exhaust fan when the target airflow is greater than an airflow threshold.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

Abstract: Example implementations relate to a method of dynamically updating a transport task of a UAV. The method includes receiving, at a transport-provider computing system, an item provider request for transportation of a plurality of packages from a loading location at a given future time. The method also includes assigning, by the transport-provider computing system, a respective transport task to each of a plurality of UAVs, where the respective transport task comprises an instruction to deploy to the loading location to pick up one or more of the plurality of packages. Further, the method includes identifying, by the transport-provider system, a first package while or after a first UAV picks up the first package. Yet further, the method includes based on the identifying of the first package, providing, by the transport-provider system, a task update to the first UAV to update the respective transport task of the first UAV.

Abstract: Embodiments herein disclose a method for optimizing power consumption in an electronic device comprising a plurality of RATs. The method includes determining a system bandwidth of the plurality of RATs available in the electronic device and mapping at least one portion of the system bandwidth to at least one power consumption level of a set of power consumption levels of the electronic device. Further, the method includes distributing the at least one portion of the system bandwidth across the plurality of RATs based on the at least one mapped power consumption level of the set of power consumption levels of the electronic device. Further, the method includes enforcing the distributed system bandwidth across the plurality of RATs in the electronic device and enabling at least one application to use the distributed system bandwidth across the plurality of RATs in the electronic device.

Abstract: Systems and methods include obtaining log data for a plurality of users of an enterprise where the log data relates to usage of a plurality of applications by the plurality of users and user metadata; analyzing the log data to determine one or more sequential patterns of application access; determining i) app-segments that are groupings of application of the plurality of applications and ii) user-groups that are groupings of users of the plurality of users, based on the log data and the one or more sequential patterns of application access; and providing access policy of the plurality of applications based on the user-groups and the app-segments. The one or more sequential patterns of application access include a sequence of accessing a plurality of applications in a given time period.

Abstract: Methods, systems, and apparatus include computer programs encoded on a computer-readable storage medium, including a method for providing content. Search results responsive to a query are identified including a first search result in a top set of search results, the first search result associated with a first entity. A first eligible content item is identified for presentation along with the search results, the first eligible content item associated with the first entity. A combined content item is identified that is a combination of the first search result and first eligible content item and is to be presented as a search result responsive to the query. The combined content item is augmented including: identifying entities related to the first entity, identifying content items that are associated with the related entities, selecting at least one identified content item, and using content from the selected content items to augment the combined content item.

Abstract: Example implementations relate to a method of dynamically updating a transport task of a UAV. The method includes receiving, at a transport-provider computing system, an item provider request for transportation of a plurality of packages from a loading location at a given future time. The method also includes assigning, by the transport-provider computing system, a respective transport task to each of a plurality of UAVs, where the respective transport task comprises an instruction to deploy to the loading location to pick up one or more of the plurality of packages. Further, the method includes identifying, by the transport-provider system, a first package while or after a first UAV picks up the first package. Yet further, the method includes based on the identifying of the first package, providing, by the transport-provider system, a task update to the first UAV to update the respective transport task of the first UAV.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: For a buck-boost DC-DC converter with n-type high-side field effect transistor (HSFET), a supply is derived from input and output rails, and this supply maintains a constant differential voltage independent of input supply voltage. The derived supply is used as the high supply (HS) of an HSFET Driver. As such, the HSFET resistance becomes independent of supply variation. A wide range ultra-low IQ (Quiescent current), edge triggered level-shifter provides support to a bootstrapped power stage of the inverting buck-boost DC-DC converter. When p-type HSFET is used, a supply is derived from the input and output supply rails, and this derived supply maintains a constant differential voltage independent to the input supply voltage. The derived supply is used as the low supply (LS) or ‘ground’ of the HSFET Driver. As such, the p-type HSFET resistance becomes independent of supply variation.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.