Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event.

Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: Apparatuses, methods and storage medium associated with virtual machine application processor startup, are disclosed herein. In embodiments, an apparatus for computing may include a plurality of processor cores; and a plurality of OS modules of an OS. The OS modules may include a BSP module and an AP module. The BSP module may be configured to write into a storage area a start state of an AP of a VM, while the VM is being started up; and the AP module may be configured to start the AP at the start state, directly in a protected mode of execution without first going through a real mode of execution. Other embodiments may be described and/or claimed.

Abstract: Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system queries a firmware interface to retrieve a potential offline set of processor cores. The operating system prevents the processor cores of the potential offline set from receiving device interrupts. The computing device detects a platform management event from the firmware interface and, in response to the platform management event, queries the firmware interface to determine a requested offline set of processor cores. Each of the processor cores in the requested offline set is included in the potential offline set. The computing device brings the processor cores of the requested offline set into a low-power state, and then the computing device may start performing a platform management operation. The platform management event may include a memory hot-plug event or a specialized workload event. Other embodiments are described and claimed.

Abstract: A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: Techniques are disclosed for configuring a server to establish a secure network communication session. An application monitors one or more resource utilization metrics of the server. Upon determining that at least one of the monitored resource metrics satisfies a specified condition, an optimization algorithm is selected based on the resource metrics and a configuration of the server. The optimization algorithm determines an updated configuration of the server while maintaining the security at par or better. The selected optimization algorithm is performed to modify determine the updated configuration of the server. Once determined, the application applies the updated configuration to the server.

Abstract: Apparatuses, methods and storage medium associated with virtual machine application processor startup, are disclosed herein. In embodiments, an apparatus for computing may include a plurality of processor cores; and a plurality of OS modules of an OS. The OS modules may include a BSP module and an AP module. The BSP module may be configured to write into a storage area a start state of an AP of a VM, while the VM is being started up; and the AP module may be configured to start the AP at the start state, directly in a protected mode of execution without first going through a real mode of execution. Other embodiments may be described and/or claimed.

Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract: Apparatuses, methods and storage media associated with managing operations of a virtual machine including dynamic idling and scheduling of virtual processors on logical processors described herein. In embodiments, an apparatus may include a physical computing platform with one or more physical processors, a virtual machine manager to manage operation of virtual machines each with a priority level and with one or more virtual processors that operate on logical processor instances of the one or more physical processors, wherein the virtual machine manager tracks activities of the virtual processors that operate on a shared logical processor instance and selectively idles and schedules one or more virtual processors in view of at least the activities of the virtual processors that operate on a shared logical processor instance and the priority of the virtual machines associated with the one or more virtual processors.

Abstract: An iBeacon compatible Bluetooth low energy device based system for monitoring objects includes a plurality of devices, a plurality of managers, and a manufacturer. Devices are attached to objects or integrated into the objects. The devices may be used for positional tracking only, or may include one or more sensors for measuring or monitoring a characteristic of the object. A device manufacturer commissions the devices with unique majors and minors. Each device is then associated with a device manager, and the device transmits messages to the manager when the device is within range of the manager. The manager determines characteristics of the object as a function of the received messages and a location (e.g., GPS coordinates) of the manager.

Abstract: Apparatuses, systems, and methods for user equipment (UE) devices to perform a radio access technology (RAT) upgrade. A UE may initiate a background scan to upgrade RAT while camped on a first system in response to an occurrence of a first condition. The first system may include a first PLMN that operates according a first RAT. The UE may determine a second system operates according to a second RAT that provides upgraded service as compared to the first RAT. The second system may be included in one or more systems found during the background scan. The UE may attempt to register on the second system based on the second PLMN operating according to the second RAT. The first and second PLMNs may each have an associated operator preference and the first PLMN may be preferred over the second PLMN.

Abstract: Apparatuses, systems, and methods for user equipment (UE) devices to perform a radio access technology (RAT) upgrade. A UE may initiate a background scan to upgrade RAT while camped on a first system in response to an occurrence of a first condition. The first system may include a first PLMN that operates according a first RAT. The UE may determine a second system operates according to a second RAT that provides upgraded service as compared to the first RAT. The second system may be included in one or more systems found during the background scan. The UE may attempt to register on the second system based on the second PLMN operating according to the second RAT. The first and second PLMNs may each have an associated operator preference and the first PLMN may be preferred over the second PLMN.

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract: A heterogeneous processor architecture is described.

Abstract: A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.

Abstract: An enhanced binder provides flexibility and certainty when selecting a version of a software library to load, and an enhanced loader prevents a library version vulnerable to a security flaw from being loaded. The binder can perform unification, implicit override, and/or redirection. Implicit override searches assembly-specific locations for an implicit_version, and override the previously chosen unification or other version with the implicit_version when the implicit_version is greater. The implicit_version gets updated with the individual assembly, whereas the unification_version gets updated with the framework. Redirection may override the implicit_version. Unlike redirection, an implicit_version does not recite an explicit range and is found outside application configuration files. The implicit_version is specified implicitly by the assembly without an XML declaration.

Abstract: Trust relationships in an online service system are established at a domain level, and propagated to components of domains as they attempt cross domain communication. In attempting to communicate across domains, a first component in a first domain attempts to validate a certificate of a second component in a second domain. Where the attempt to validate the certificate indicates that a trust relationship does not exist between the first component and the second domain, the first component determines whether a domain level trust relationship exists between the two domains. The first component propagates the trust status between the first and second domains to itself. If there is an existing trust relationship between the first and second domains, the first component validates the certificate of the second component in response. The second component executes the same process to complete the connection.