Patents by Inventor Gautam V. Thakar

Gautam V. Thakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803661
    Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: October 12, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam V. Thakar, Reima T. Laaksonen, Cameron Gross, Eric A. Joseph
  • Publication number: 20040191999
    Abstract: Fabricating a semiconductor includes forming a conductive layer outwardly from a surface of a substrate. A mask layer comprising a hard mask is deposited outwardly from the conductive layer to pattern the conductive layer to form a gate stack. The conductive layer is etched to remove the conductive layer from the surface of the substrate and to form the gate stack, where the mask layer is disposed outwardly from the gate stack. Ions are implanted outwardly from the surface of the substrate, where the mask layer prevents at least a portion of the ions from penetrating the gate stack while penetrating the substrate.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Applicant: Texas Instruments Incroporated
    Inventors: Pr Chidambaram, Srinivasan Chakravarthi, Gautam V. Thakar, Toan Tran
  • Publication number: 20040092089
    Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
    Type: Application
    Filed: August 21, 2003
    Publication date: May 13, 2004
    Inventors: Gautam V. Thakar, Reima T. Laaksonen, Cameron Gross, Eric A. Joseph
  • Patent number: 6624068
    Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam V. Thakar, Reima T. Laaksonen, Cameron Gross, Eric A. Joseph
  • Publication number: 20030040179
    Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
    Type: Application
    Filed: August 24, 2001
    Publication date: February 27, 2003
    Inventors: Gautam V. Thakar, Reima T. Laaksonen, Cameron Gross, Eric A. Joseph