Abstract: In some embodiments, a computer accessible medium comprises a plurality of instructions which, when executed, probe nodes in a network to determine if one or more nodes are experiencing any events indicative of a fault. The nodes are probed in a sequence. The instructions, when executed, in response to receiving a first alert transmitted by a first node in the network asynchronous to the probes performed according to the sequence, probe one or more neighbor nodes of the first node. In some other embodiments, the instructions, when executed, in response to receiving a first alert transmitted by a first node in the network asynchronous to the probes performed according to the sequence, interrupt probing according to the sequence to probe at least the first node.

Abstract: Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.

Abstract: Methods, systems and programs for isolating faults in a network loop is described. The link between the last device and the initiator in the network loop is tested. The loop segment between the initiator and the last device in the network loop is testesd. If a faulty link is identified in the loop segment between the initiator and the last device, then a faulty loop segment is identified and the faulty link within the faulty loop segment is isolated. For various embodiment of the present invention, divide and conquer testing or other systematic testing methods may be used to isolate the faulty link.

Abstract: Methods, systems and programs for isolating faults in a network loop are described. A single write and multiple read test is performed on the last device in a network loop to determine whether the link between the last device and the initiator is a faulty link. A multiple write test is performed on the last device to determine whether the loop segment between the initiator and the last device includes at least one faulty link. If a write error is identified, then the low level error counters of each network device are monitored. The network device with the updated error counter is identified such that the device before that network device in the network loop is selected as the first test device to be used in isolating a faulty link between the initiator and the last device.

Abstract: Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.

Abstract: Provided is a computer implemented method, system, and program for determining system information, wherein the system is comprised of at least one host adaptor, switch, and storage device. A path in the system from one host adaptor to the I/O device includes as path components one host adaptor, one switch, one storage device, a first link between the host adaptor and the switch and a second link between the switch and the storage device. A determination is made of component information on host adaptor, switch, and I/O device components in a network system. The determined component information is added to a configuration file providing configuration information on the system. For each determined host adaptor, a determination is made from the component information of information on the first link between the host adaptor and the switch and on the I/O device to which the host adaptor communicates.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system comprises a plurality of nodes an-d a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.