Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Abstract: A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.