Patents by Inventor Gayathri Rao
Gayathri Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783966Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: October 4, 2019Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20200035300Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 10446229Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: February 12, 2018Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20180182456Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: February 12, 2018Publication date: June 28, 2018Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 9892785Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: February 24, 2017Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20170169886Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 9583187Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: March 28, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Patent number: 9530523Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.Type: GrantFiled: June 25, 2014Date of Patent: December 27, 2016Assignee: Intel CorporationInventors: Gayathri Rao Subbu, Kiran Pangal, Nathan Franklin
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Publication number: 20160284404Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: March 28, 2015Publication date: September 29, 2016Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20150380111Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.Type: ApplicationFiled: June 25, 2014Publication date: December 31, 2015Applicant: Intel CorporationInventors: GAYATHRI RAO SUBBU, KIRAN PANGAL, NATHAN FRANKLIN
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Publication number: 20150206082Abstract: Methods, systems, computer-readable media, and apparatuses for identifying employee capacity issues for performing document review are presented. In some embodiments, a computing device may categorize delegations of authority for a plurality of employees. Subsequently, the computing device may group a volume of documents into a plurality of groups by their monetary value. The computing device may then calculate the required employee capacity and the actual employee capacity available to assess each group of documents. Subsequently, the computing device may compare the actual employee capacity with the required employee capacity for each group of documents and determine, based on the comparison, whether a difference exists between the actual employee capacity and the required employee capacity. In response to determining that a difference exists, the computing device may provide one or more resolution.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Bank of America CorporationInventors: Gayathri Rao Sarvepalle, Leena Mahavar, Shantanu Singh, Tanveer Sajanlal, Sandeepan Thapliyal
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Patent number: 6663713Abstract: A method and apparatus are disclosed for forming thin polymer layers on semiconductor substrates. In one embodiment, the method and apparatus include the vaporization of stable di-pxylylene, the pyrolytic conversion of such gaseous dimer material into reactive monomers, and the optional blending of the resulting gaseous p-xylylene monomers with one or more polymerizable materials in gaseous form capable of copolymerizing with the p-xylylene monomers to form a low dielectric constant polymerized parylene material. An apparatus is also disclosed which provides for the distribution of the polymerizable gases into the deposition chamber, for cooling the substrate down to a temperature at which the gases will condense to form a polymerized dielectric material, for heating the walls of the deposition chamber to inhibit formation and accumulation of polymerized residues thereon, and for recapturing unreacted monomeric vapors exiting the deposition chamber.Type: GrantFiled: October 22, 1996Date of Patent: December 16, 2003Assignee: Applied Materials Inc.Inventors: Stuardo A. Robles, Visweswaren Sivaramakrishnan, Bang C. Nguyen, Gayathri Rao, Gary Fong, Vicente Lam, Peter Wai-Man Lee, Mei Chang
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Patent number: 5958510Abstract: A method and apparatus are disclosed for forming thin polymer layers on semiconductor substrates. In one embodiment, the method and apparatus include the sublimation of stable dimer parylene material, the pyrolytic conversion of such gaseous dimer material into reactive monomers, and for the optional blending of the resulting gaseous parylene monomers with one or more polymerizable materials in gaseous form capable of copolymerizing with the parylene monomers to form a low dielectric constant polymerized parylene material. An apparatus is also disclosed which provides for the distribution of the polymerizable gases into the deposition chamber, for cooling the substrate down to a temperature at which the gases will condense to form a polymerized dielectric material, for heating the walls of the deposition chamber to inhibit formation and accumulation of polymerized residues thereon, and for recapturing unreacted monomeric vapors exiting the deposition chamber.Type: GrantFiled: January 8, 1996Date of Patent: September 28, 1999Assignee: Applied Materials, Inc.Inventors: Visweswaren Sivaramakrishnam, Bang C. Nguyen, Gayathri Rao, Stuardo Robles, Gary L. Fong, Vicente Lim, Peter W. Lee