Abstract: Systems and methods are disclosed for processing information related to a terminal operating system. In one exemplary implantation, there is provided a method for providing information of terminal operating system management. The method may include processing information related to an input to manage the terminal operating system management. Other exemplary implementations may include processing to generate a result such that an output of a result of the managed terminal operating system management functionality is produced.

Abstract: Systems and methods are disclosed associated with processing information involving terminal operating systems. According to one illustrative implementation, an exemplary method for processing information involving terminal operating system herein may include processing data in a TOS format associated with a TOS type, converting the data into a TOS agnostic format, and performing processing using the TOS agnostic data.

Abstract: Systems and methods are disclosed for processing information related to a terminal operating system. In one exemplary implantation, there is provided a method for providing information of terminal operating system management. The method may include processing information related to an input to manage the terminal operating system management. Other exemplary implementations may include processing to generate a result such that an output of a result of the managed terminal operating system management functionality is produced.

Abstract: Systems and methods are disclosed associated with processing information involving terminal operating systems. According to one illustrative implementation, an exemplary method for processing information involving terminal operating system herein may include processing data in a TOS format associated with a TOS type, converting the data into a TOS agnostic format, and performing processing using the TOS agnostic data.

Abstract: Systems and methods are disclosed for processing information related to appointment systems as well as associated terminal operating systems and other related systems. According to one illustrative implementation, an exemplary method for processing information involving appointment systems herein may include receiving/handling/processing data in a TOS format associated with a TOS type, converting the data into a TOS agnostic format, and performing processing using the TOS agnostic data. In another exemplary implementation, there is provided computer-implemented methods for processing information for appointment systems in conjunction with associated systems and operations. Systems and computer-implemented methods herein may include or involve processing information related to an appointment system and interrelationships with associated terminal operating systems, gate systems, and/or various TOS-agnostic features and functionality.

Abstract: Systems and methods are disclosed for processing information related to a terminal operating system. According to one illustrative implementation, an exemplary method for processing information involving terminal operating system herein may include processing data in a TOS format associated with a TOS type, converting the data into a TOS agnostic format, and performing processing using the TOS agnostic data. In another exemplary implementation, there is provided a method for providing information of terminal operating system management. The method may include processing information related to an input to manage the terminal operating system management. Other exemplary implementations may include processing to generate a result such that an output of a result of the managed terminal operating system management functionality is produced.

Abstract: A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate.

Abstract: A system (100) for processing simplex and multiplexed voice packets transmitted over a network is disclosed. The system (100) may include a processor (102) and a compare section (104). A compare section (104) may include simplex entries (110-0) and multiplex entries (110-1). The compare section (104) can compare voice packet information with simplex entries (110-0) and multiplex entries (110-1) simultaneously to correlate voice packet data with a given voice channel.

Abstract: A system (100) for receiving data from an asynchronous network and transmitting such data onto a synchronous network includes a voice packet buffer memory system (108) with a jitter buffer (118) having groups of entries storing data for voice channels and jitter buffer valid bit (JBVB) memory (120) for status of a particular entry for multiple jitter buffer groups. Writing or reading data from a jitter buffer entry sets a corresponding JBVB memory bit to a valid or invalid state respectively. Jitter buffer data may be read with a corresponding state memory bit. If a corresponding JBVB memory bit is valid, data from a jitter buffer (118) may be provided as an output. If a corresponding JBVB memory bit is invalid, a loss recovery algorithm may compensate for such invalid jitter buffer data.

Abstract: A semiconductor memory device is provided as well as a method for operating the semiconductor memory device. The memory device includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell of the NOR array involves a single transistor, similar to each cell of the NAND array. The memory device is, therefore, an integrated circuit that includes not only the NOR and NAND arrays, but also the row and column decoders corresponding to each array. Furthermore, the integrated circuit includes the interface circuitry needed to transfer information as pages into and from the NAND array. The corresponding interface or controller is implemented on the same monolithic substrate as both the NAND array and the NOR array. Addresses targeted for the NOR array are sent as fully memory-mapped data into the NOR array, whereas addresses targeted for the NAND array are sent through the controller integrated within the semiconductor memory device.