Patents by Inventor Geetha Arthanari

Geetha Arthanari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ASIC clock floor planning method and structure
    Patent number: 7454735
    Abstract: A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Geetha Arthanari, Keith M. Carrig, Mark R. Lasher, Daniel R. Menard
  • Asic clock floor planning method and structure
    Publication number: 20060031699
    Abstract: A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks 110; positioning a temporary reference insertion point (TIP) 120; grouping the sinks together with structured clock buffers (SCBs) in a set of levels 140; and moving the SCBs to improve symmetry of the tree 150. The SCBs may be of several sizes and may be positioned horizontally 42 or vertically 45 and moved within limits 46 to permit the program to calculate a complete tree.
    Type: Application
    Filed: December 17, 2002
    Publication date: February 9, 2006
    Inventors: Geetha Arthanari, Keith Carrig, Mark Lasher, Daniel Menard